In this paper average power consumption, write access time, read access time and retention time of dram cell designs have been analyzed for the nano-meter scale memories. Many modern day processors use dram cell for on chip data and program memory storage. The major power in dram is the off state leakage current. Improving on the power efficiency of a dram cell is critical for the improvement in average power consumption of the overall system. 3T dram cell, 4T dram and 3T1D DRAM cells are designed with the schematic design technique and their average power consumption are compared using TANNER EDA tool .average power consumption, write access time, read access time and retention time of 4T, 3T dram and 3T1D DRAM cell are simulated and compared on 32 nm technology.

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An improved trapezoidal pile gate bulk FinFET device is implemented with an extension in the gate for enhancing the performance. The novelty in the design is trapezoidal crosssection FinFET with stacked metal gate along with extension on both sides. Such improved device structure with additional process cost exhibits significant enhancement in the performance metrics specially in terms of leakage current behavior. The simulation study proves the suitability of the device for low power applications with improved on/off current ratio, subthreshold swing (SS), drain induced barrier lowering (DIBL), Gate Induced Drain Leakage (GIDL) uniform distribution of electron charge density along the channel and effects of Augur recombination within the channel.

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