Design and implementation of low power SRAM structure using nanometer scale

Mishra, Loveneet; Kumar, Sampath; Mangesh, Sangeeta

doi:10.1109/aeeicb.2016.7538407

Cited by 4 publications

(2 citation statements)

References 8 publications

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“…[ 9 – 11 ]. Over the years, different cell structures or operation techniques [ 12 – 16 ] have been proposed for minimizing power consumption in SRAMs. Some of the newly proposed cells incorporate non-volatile storage elements, such as resistive random access memory (RRAM) and magnetoresistive random access memory (MRAM) [ 17 – 20 ], to achieve zero-holding power while maintaining low operation power and fast accessing speed in processing volatile data.…”

Section: Introductionmentioning

confidence: 99%

A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

et al. 2017

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This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for maintaining fast accessing speed. Data can be non-volatilely stored in new SRAM cell through a unique self-inhibit operation onto the resistive random access memory (RRAM) load, achieving zero static power during data hold.

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Section: Introductionmentioning

confidence: 99%

A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

et al. 2017

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“…The SRAM 8T cell is shown in Figure 3. These power supply sources diminish the voltage swing at the output node when write operation is being performed [7]. Figure 3 shows the circuit diagram of SRAM 8T cell.…”

Section: Sram 8t Cellmentioning

confidence: 99%

High-Speed Electronic Memories and Memory Subsystems

Asthana¹,

Mishra²

2018

Advanced Electronic Circuits - Principles, Architectures and Applications on Emerging Technologies

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Memories have played a vital role in embedded system architectures over the years. A need for high-speed memory to be embedded with state-of-the-art embedded system to improve its performance is essential. This chapter focuses on the development of highspeed memories. The traditional static random access memory (SRAM) is first analyzed with its different variant in terms of static noise margin (SNM); these cells occupy a larger area as compared to dynamic random access memory (DRAM) cell, and hence, a comprehensive analysis of DRAM cell is then carried out in terms of power consumption, read and write access time, and retention time. A faster new design of P-3T1D DRAM cell is proposed which has about 50% faster reading time as compared to the traditional three-transistor DRAM cell. A complete layout of the structure is drawn along with its implementation in a practical 16-bit memory subsystem.

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