Design and implementation of 64 bit multiplier using vedic algorithm

Jais, Amish; Palsodkar, Prasanna

doi:10.1109/iccsp.2016.7754250

Cited by 17 publications

(5 citation statements)

References 9 publications

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“…A 2‐bit Vedic multiplier is able to receive two 2‐bit numbers A = a 1 a 0 and B = b 1 b 0 and output their product as a 4‐bit number P = p 3 p 2 p 1 p 0 (see Equation (1)).

\begin{array}{l} p_{0} goodbreak= a_{0} . b_{0} \\ p_{1} goodbreak= ((), a_{0} . b_{1}) \oplus ((), a_{1} . b_{0}) \\ p_{2} goodbreak= ((), a_{0} . b_{1}) . ((), a_{1} . b_{0}) \oplus ((), a_{1} . b_{1}) goodbreak= C 1 \oplus ((), a_{1} . b_{1}) \\ p_{3} goodbreak= C_{2} goodbreak= ((), a_{0} . b_{1}) . ((), a_{1} . b_{0}) \\ {Symbol}^{'} \oplus^{'} ndicates Ex goodbreak- OR operation \end{array}

As can be seen in Figure 8, a 4‐bit Vedic multiplier can be implemented using four 2‐bit Vedic multipliers and three 4‐bit ripple carry adder (RCA) 38,39 …”

Section: Vedic Multiplier Architecturementioning

confidence: 99%

“…Their addition is accomplished using UT Sutra, and the intermediate result of this procedure is known as parallelism. 38,39 The logical representation of the 2-bit Vedic multiplier has been depicted in Figure 7.…”

Section: Vedic Multiplier Architecturementioning

confidence: 99%

“…As can be seen in Figure 8, a 4-bit Vedic multiplier can be implemented using four 2-bit Vedic multipliers and three 4-bit ripple carry adder (RCA). 38,39…”

Section: Vedic Multiplier Architecturementioning

confidence: 99%

“…The UT Sutra was made based on a novel idea that allows for the simultaneous addition of all partial products to generate the full set of products. Their addition is accomplished using UT Sutra, and the intermediate result of this procedure is known as parallelism 38,39 . The logical representation of the 2‐bit Vedic multiplier has been depicted in Figure 7.…”

Section: Vedic Multiplier Architecturementioning

confidence: 99%

See 3 more Smart Citations

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

Noorallahzadeh

Mosleh

Ahmadpour

et al. 2023

Int J Numerical Modelling

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Reversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N1, N2, and N3, which are used to develop a novel effective 2‐bit PP reversible Vedic multiplier and 4‐bit ripples carry adders (RCAs). Moreover, 2‐bit Vedic multiplier and RCA are used to develop the 4‐bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state‐of‐the‐art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two‐bit and four‐bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.

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“…A 2‐bit Vedic multiplier is able to receive two 2‐bit numbers A = a 1 a 0 and B = b 1 b 0 and output their product as a 4‐bit number P = p 3 p 2 p 1 p 0 (see Equation (1)).

\begin{array}{l} p_{0} goodbreak= a_{0} . b_{0} \\ p_{1} goodbreak= ((), a_{0} . b_{1}) \oplus ((), a_{1} . b_{0}) \\ p_{2} goodbreak= ((), a_{0} . b_{1}) . ((), a_{1} . b_{0}) \oplus ((), a_{1} . b_{1}) goodbreak= C 1 \oplus ((), a_{1} . b_{1}) \\ p_{3} goodbreak= C_{2} goodbreak= ((), a_{0} . b_{1}) . ((), a_{1} . b_{0}) \\ {Symbol}^{'} \oplus^{'} ndicates Ex goodbreak- OR operation \end{array}

As can be seen in Figure 8, a 4‐bit Vedic multiplier can be implemented using four 2‐bit Vedic multipliers and three 4‐bit ripple carry adder (RCA) 38,39 …”

Section: Vedic Multiplier Architecturementioning

confidence: 99%

Section: Vedic Multiplier Architecturementioning

confidence: 99%

“…As can be seen in Figure 8, a 4-bit Vedic multiplier can be implemented using four 2-bit Vedic multipliers and three 4-bit ripple carry adder (RCA). 38,39…”

Section: Vedic Multiplier Architecturementioning

confidence: 99%

Section: Vedic Multiplier Architecturementioning

confidence: 99%

See 2 more Smart Citations

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

Noorallahzadeh

Mosleh

Ahmadpour

et al. 2023

Int J Numerical Modelling

View full text Add to dashboard Cite

show abstract

“…Jais, A. [15], Palsodkar [15] proposed a very eventual 64 bit ancient multiplier which enhances the performance of DSP processors and shortens the complexity, consumption of power, area and delay. Results obtained are found with 33% reduction in delay.…”

Section: Literature Surveymentioning

confidence: 99%

Urdhva Tiryak Sutra Based Ancient Multiplication in Reversible Logic Circuits

Saranya*,

Priya,

Priyadharshini

et al. 2020

IJITEE

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The proposed work analyses the employment of an ancient mathematical approach for building an arithmetic logic unit. Dissipation of power is one of the major driving issues in VLSI design. With the assistance of reversible gates, the power dissipation and loss of information can be minimized. The speed and accuracy of the Arithmetic Logic Unit depends on the propagator. Employing the traditional mathematics sutras technique within the computation algorithm reduces the complexity, duration and power. Due to the effect of environmental factors on the digital circuits, parity conserving technique is incorporated for providing error detection ability. The proposed work deal with the design and analysis of 32 bit reversible multiplier using ancient sutras with and without parity conserving technique .The planned work is implemented on Xilinx ISE Spartan 6E series of FPGA and simulation results are obtained. By using Cadence EDA tool, power, area and delay are calculated. The quantum parameters are calculated manually for 32-bit reversible multiplier using ancient technique with and without parity conserving technique using Urdhva Tiryakbhyam sutra.

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