Design and implementation of a novel nine‐level MT‐MLI with a self‐voltage‐balancing switching technique

Naik, Banavath Shiva; Suresh, Y.; Venkataramanaiah, J.; Panda, Anup Kumar

doi:10.1049/iet-pel.2018.6119

Cited by 20 publications

(4 citation statements)

References 22 publications

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“…22 Another topology to generate the desired output voltage at the cost of a higher number of power switches is discussed. 23 A nine-level MLI is proposed in Naik et al 24 which has an ability to get a self-balancing voltage across the capacitor. However, boosting is missing.…”

Section: Switched-capacitor (Sc) MLImentioning

confidence: 99%

Evaluation of a grid‐connected reduced‐component boost multilevel inverter (BMLI) topology

Debela

Singh

Sood

2022

Circuit Theory & Apps

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In this paper, a reduced‐component switched‐capacitor boost multilevel inverter (SC‐BMLI) topology is proposed for off‐grid and on‐grid applications. Recently, switched‐capacitor‐based multilevel inverter (MLI) topologies have been employed to avoid the need for multiple isolated direct current (DC) sources when compared with traditional cascaded MLIs. To generate a nine‐level stepped‐up voltage across the load, the SC‐BMLI needs only eight power switches and two capacitors. To get the appropriate nine‐level switching pattern, phase disposition pulse width modulation (PD‐PWM) has been used. An extended 13‐level boost multilevel inverter (BMLI) is also discussed in this paper. The proposed topology is connected to the grid to control the grid current using synchronous reference frame‐based proportional–integral controller. A small‐signal modeling and analysis has been discussed in detail for the phase‐locked‐loop (PLL). Moreover, to prove the superior performance of the SC‐BMLI, comparative analysis with an existing single DC source MLI has also been performed. The feasibility of the 9‐level and 13‐level proposed topologies, with and without the grid‐connection, is evaluated by Matlab/Simulink simulation and verified by an experimental study using the OPAL‐RT 4510 real‐time platform. Further, prototype model of nine‐level BMLI has been developed in the laboratory using DSpace 1103 controller and results are compared with simulation.

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Section: Switched-capacitor (Sc) MLImentioning

confidence: 99%

Evaluation of a grid‐connected reduced‐component boost multilevel inverter (BMLI) topology

Debela

Singh

Sood

2022

Circuit Theory & Apps

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“…Basic fundamental frequency switching, sinusoidal PWM, selective harmonic elimination pulse width modulation (SHE-PWM), and space vector PWM (SV-PWM) are some of the modulation schemes 21 used by converter topologies to provide a sinusoidal staircase output voltage waveform, and some of the other modulation schemes mentioned in previous studies. 22,23 Later to create gate pulses for switching devices, a PD-SPWM switching approach was used. To create pulses, level-shifted triangle pulses with the same phase get mated with only an ideal sinusoidal signal.…”

Section: Power Loss Calculationmentioning

confidence: 99%

A capacitor based single source MLI with natural balancing and less component for EV/HEV application

Suresh

Naik

Rao

et al. 2022

Circuit Theory & Apps

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Summary Due to their remarkable performance, capacitor‐based inverters have recently gained attention. Hence, a new capacitor‐based multilevel inverter is presented in this paper for electric and hybrid electric vehicle (EV and HEV) applications. EV systems are quite well for their use of two‐level inverters; however, the generated load voltage comprises substantial undesirable harmonic content. It is regarded as one of the most efficient methods since replacing a two‐level inverter with a multilevel inverter improves the power quality despite significantly reducing total harmonic distortion. Therefore, the recommended filter dimension will also be minimized. A flurry of reliability concerns has arisen due to the increased number of devices, circuit complexity, and stress on the circuit devices. A nine‐level voltage waveform is created with only ten IGBTs, a DC‐Source, and two capacitors. In the proposed nine‐level inverter, the capacitor voltage is balanced utilizing a simple control approach to regulate the flying capacitor (FC) voltages actively. Here described a simple logic gate‐based pulse‐width modulation technique that ensures capacitor power balancing. The proposed inverter operation and capability are validated by experimental results derived from a laboratory prototype. Finally, by contrasting the new and standard inverter topologies, the virtues of the suggested architecture by the number of devices and price of the equipment are highlighted, and it is a simpler structure that requires less space and footprint area.

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“…Fundamental frequency switching (nearest level control), selective harmonic elimination pulse width modulation (SHE-PWM), sinusoidal PWM, space vector PWM, and other [27][28][29] switching techniques are used in multilevel inverters to produce staircase output waveforms. Fundamental frequency PWM (FF-PWM) control strategy is used to generate the gating signals to the semiconductors.…”

Section: Modulation Strategymentioning

confidence: 99%

A novel nine‐level boost inverter with a low component count for electric vehicle applications

Naik

Suresh

Rao

2021

Int Trans Electr Energ Syst

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Summary In electric vehicles (EVs), considerable battery cells are cascaded in series for motor driving to improve the output voltage. The series combination of battery cells causes challenges like isolation of faulty cells, voltage unbalance, and slow charge equalization. Therefore, state‐of‐charge (SOC) and voltage equalization circuits are often used in industries to protect the battery cells. A nine‐level inverter circuit with a double voltage boost is proposed to reduce the above issues based on the switch‐capacitor (SC) principle. Unique features like self‐balancing, voltage boosting are attained, which cannot be achieved through traditional inverters. The proposed topology can operate at a wide range of modulation indices (ma) to produce different voltage levels. The absence of a back‐end H‐bridge in the proposed circuit offers low voltage stress across the semiconductors. The operating principle, capacitor sizing, and modulation approach are presented. Further, experimental tests are conducted at different loading conditions to verify the performance of the proposed circuit.

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Design and implementation of a novel nine‐level MT‐MLI with a self‐voltage‐balancing switching technique

Cited by 20 publications

References 22 publications

Evaluation of a grid‐connected reduced‐component boost multilevel inverter (BMLI) topology

Evaluation of a grid‐connected reduced‐component boost multilevel inverter (BMLI) topology

A capacitor based single source MLI with natural balancing and less component for EV/HEV application

A novel nine‐level boost inverter with a low component count for electric vehicle applications

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