Design and Implementation of a Modular and Portable IEEE 754 Compliant Floating-Point Unit

Abstract

Multimedia and communication algorithms from embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floating-point hardware, final implementations of these algorithms are usually carried out using floating-point emulation in software, or conversion (manually or automatically) of the floating-point operations to fixed point operations. Such strategies often lead to semioptimal and imprecise software implementation. This paper presents the design and implementation of a Floating-Point Unit (FPU) for an Application Specific Instruction set Processor (ASIP) suitable for embedded systems domain. Using a state-of-the-art Architecture Description Language (ADL) based ASIP design framework, the FPU is implemented in such a modular way that it can be easily adapted to any otherRISC like processor. The implemented operations are fully compliant to the IEEE 754 standard which facilitates portable software development. The benchmarking, in terms of energy, area and speed, of the designed FPU highlights the trade-offs of having a hardware FPU w.r.t. software emulation of floating-point operations.

Are Ieee 754 32-Bit and 64-Bit Binary Floating-Point Accurate Enough?

“…All the research papers consulted in this research [5,[19][20][21]. [3][4][14][15]18,[21][22][23][24][28][29] did not provide direct relationship between the width of fraction and the width of available unsigned registers in determining the upper bound of accuracy of decimal fraction computed within binary floating-point. We establish the direct relation-ships between y fraction bits and z bit of unsigned integral registers in the statement (8) and (9) On the reverse direction z bit unsigned integral register will be capable of representing decimal-digits fraction accurately without sophisticated algorithm.…”

“…Then the hardware computes the x fraction bits as if they are integral values [2,14,[17][18]. The decimal fraction is gained by integral division, with the former divided by the latter.…”

“…Single-precision has 8 power bits, double-precision has 11. Single-precision has 23 fraction bits, double-precision has 52 fraction bits [12][13][14][15] (Figure 1). …”

Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers

“…In [22] the use of the LISA tools is described to integrate an FPU directly into the ASIP architecture to extend the instruction set with floating point instructions.…”