Design and Implementation of a Low Power Ternary Full Adder

Abstract

In this work, the design and implementation of a low power ternary full adder are presented in CMOS technology. In a ternary full adder design, the basic building blocks, the positive ternary inverter (PTI) and negative ternary inverter (NTI) are developed using a CMOS inverter and pass transistors. In designs of PTI and NTI, W/L ratios of transistors have been varied for their optimum performance. The ternary full adder and its building blocks have been simulated with SPICE 2G.6 using the MOSIS model parameters. The rise and fall times of PTI show an improvement by a factor of 14 and 4, respectively, and that of the NTI by a factor of nearly 4 and 17, respectively over that of earlier designs implemented in depletion-enhancement CMOS (DECMOS) technology. The noise margins improve by a factor of nearly 2 in PTI and NTI, respectively.The ternary full adder has been fabricated in MOSIS two micron n-well CMOS technology. The full adder and its building blocks, NTI and PTI have been tested experimentally for static and dynamic performance, compared with the SPICE simulated behavior, and close agreement is observed.The ternary-valued logic circuits designed in the present work which do not use depletion mode MOSFETS perform better than that implemented earlier in DECMOS technology. The present design is fully compatible with the current CMOS technology, uses fewer components and dissipates power in the microwatt range.

Can Ternary Computing Improve Information Assurance?

“…Srivastava et al has shown that balanced ternary full adders can be designed with CMOS using a dual power supply [29]. Balla et al also presented the design of a MOS ternary logic family [30].…”

Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics

“…It is worth mentioning that the proposed method of designing ternary structures significantly reduces the number of the transistors of the ternary Full Adder cell and do not require any additional power supplies. For instance the conventional CMOS ternary Full Adder cell [20] is composed of more than 200 transistors and needs an additional voltage supply. As an another instance the state-of-the-art CNTFET-based ternary Full Adder cell, which can be considered as two cascaded CNTFET-based ternary Half Adders [6] is composed of 190 CNTFETs and requires an extra voltage supply.…”

Multiplier Design Utilizing Tri Valued Logic for RLNS Based DSP Applications

“…However the most efficient radix for implementing switching systems is claimed to be the natural base (e = 2.71823). This infers that the best integral radix is 3 rather than 2 [20] [28]. From the previously proposed works the design of basic ternary logic gates and its application in various circuits can be studied [29]- [32].…”

“…From the literature survey, it has been observed that in two-level logic (binary logic), performance degradation occurs due to large area occupied for interconnection purpose [20]. It is broadly studied that in VLSI chip 70% of the area is consumed for interconnection, 20% to insulation and 10% to devices [21].…”