Design and Implementation of a Latency Efficient Encoder for LTE Systems

Abstract

The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8‐bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure.

Iterative Suboptimal Maximum Likelihood Receiver for Nonlinearly Distorted SC-FDMA Symbols

“…Therefore, among other challenges it is crucial to minimize the impact of nonlinear amplification, especially for mobile terminals. In LTE, the radio access for the uplink is based on single carrier frequency division multiple access (SC-FDMA) [1,2]. The reason is that not only it features small variations in the instantaneous power of the transmitted signal but also the possibilities for both FDMA with flexible bandwidth assignment and low-complexity equalization in the frequency domain [3].…”