A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, we propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix multiplications, we derive a well-organized recursive formula and realize a pseudorandom sequence generator with multiple outputs. Experimental results show that, although the total area of the proposed scheme is 3% to 13% larger than that of the existing scheme, our parallel architecture improves the throughput by 2, 4, and 6 times compared with the existing scheme based on a single output. In addition, we apply our approach to a 2×2 multiple input/multiple output (MIMO) detector targeting the 3rd Generation Partnership Project Long Term Evolution (3GPP LTE) system. Therefore, the throughput of the MIMO detector is significantly enhanced by parallel processing of data communications.Keywords: pseudorandom sequence generator, linear feedback shift register, matrix multiplication, 3GPP LTE system, MIMO detector. Manuscript received Sept. 4, 2009; revised Dec. 17, 2009; accepted Jan. 4, 2010. This work was supported by the IT R&D program of MKE/KEIT, Rep. of Korea [2006-S-001-04 I. IntroductionPseudorandom sequences [1] have been widely used in various fields, including communications, navigation, radar technology, cipher technologies, remote control, measurements, and industrial automation [2]. For example, pseudorandom sequences have been used in error-correcting codes [3], spread spectrum communication [4], [5], and system identification and parameter measurements [6], [7]. Other example applications are found in surface characterization and 3D scene modeling [8]. The design of a general purpose pseudorandom sequence generator has matured and has already been commercialized [9]-[11].Pseudorandom sequences are series of 1's and 0's that lack any definite pattern and look statistically independent and uniformly distributed. The sequences are deterministic, but exhibit noise properties similar to randomness [12]. In particular, a pseudorandom sequence generator is usually made up of shift registers with feedback. By linearly combining elements from taps of the shift register and feeding them back to the input of the generator, we can obtain a sequence of much longer repeat length using the same number of delay elements in the shift register. Therefore, these blocks are also referred to as a linear feedback shift register (LFSR) [13], [14]. The length of the shift register, the number of taps, and their positions in the LFSR are important to generate pseudorandom sequences with desirable auto-correlation properties [15]. However, the output of the conventional pseudorandom sequence generator is limited to 1 bit per clock cycle. This restriction can be a bottleneck for data communications and may cause a delay. have been proposed [16], [17]. The approaches describe a parallel architecture implementation of a pseudorandom...

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The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8‐bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure.