Design and Implementation of a Field Programmable CRC Circuit Architecture

Toal, C.; McLaughlin, Kieran; Sezer, Sakir; Yang, Xin

doi:10.1109/tvlsi.2008.2008741

Cited by 25 publications

(11 citation statements)

References 10 publications

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“…Toal and his team proposed architecture using field reprogrammable chips so that it is fully flexible in terms of the polynomial deployed and the input port width. They synthesized circuit and mapped it to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology which is capable of supporting line speeds of 5 Gb/s [29].…”

Section: 14mentioning

confidence: 99%

Configurable CRC Error Detection Model for Performance Analysis of Polynomial: Case Study for the 32-Bits Ethernet Protocol

Gad

Naik

2015

Lecture Notes in Computer Science

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Abstract. Almost every form of digital information exchange can introduce communication errors. In order to overcome the inherent inaccuracy of information transmission, a few methods for error detection and correction have been developed. Cyclic Redundancy check Codes (CRCs) are used in embedded networks for effective error detection. Paper discusses the development of the simulation model for the configurable CRC-polynomials performance analysis over Binary Symmetric Channels (BSCs). This paper presents a novel model which can be used to investigate several classes of CRC polynomials codes with 'n' parity bits varying from '1' to '64'. It also discuss the hardware implementation on Altera's FPGA Stratix II GX device 'EP2SGX90FF1508C3' for CRC-32 'IEEE-802' and suggest the indirect methodology of CRC-performance using Packet Error Rate (PER) parameter using Altera TSE MegaCore function that supports 10/100/1000 Mbps Ethernet over 1000Base-LX physical media. It is proposed to search good CRC codes of 32, 40 and 64 bit and studying performance for maximum payload over Ethernet protocol.

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Section: 14mentioning

confidence: 99%

Configurable CRC Error Detection Model for Performance Analysis of Polynomial: Case Study for the 32-Bits Ethernet Protocol

Gad

Naik

2015

Lecture Notes in Computer Science

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“…We found only two other hardware implementations [8], [9] that can support very limited number of generator polynomials. The re-generation in [8] is achieved with Galois Field Multiplication and Accumulation (GFMAC) with soft-coded and hard-coded generator polynomials.…”

Section: Related Workmentioning

confidence: 99%

“…Unfortunately, the reconfiguration time is not provided. The implementation [9] can process variable number of 32 bit generator polynomials, and can be modified to support 64 bit, but cannot support both at the same time in one circuit. The maximum throughput for processing 32 bits with a 32 bit generator polynomial is 4.92 Gbps.…”

Section: Related Workmentioning

confidence: 99%

“…There are only two adaptable hardware implementa- tions with limited support for a number of generator polynomials [8], [9]. They differ from our implementation in that they require separate implementation for every generator polynomial, while our circuits support variable number of CRC standards with only one implementation.…”

Section: Comparison To Related Workmentioning

confidence: 99%

“…Unfortunately, the reconfiguration time and area utilization are not provided. [9] is generic in its design, thus it can be scaled to process 64, 128 or 256 bits, with maximal theoretical throughput of 40 Gbps at 256 bits. It is 6x slower compared with our adaptable Slicing-by-8 implementation, and 5x slower compared with adaptable Slicing-by-16.…”

Section: Comparison To Related Workmentioning

confidence: 99%

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High-Speed Fully-Adaptable CRC Accelerators

Akagić

Amano

2013

IEICE Trans. Inf. & Syst.

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Amila AKAGIC†a) , Nonmember and Hideharu AMANO †b) , Member SUMMARY Cyclic Redundancy Check (CRC) is a well known error detection scheme used to detect corruption of digital content in digital networks and storage devices. Since it is a compute-intensive process which adversely affects performance, hardware acceleration using FPGAs has been tried and satisfactory performance has been achieved. However, recent extended usage of networks and storage systems require various correction capabilities for various CRC standards. Traditional hardware designs based on the LFSR (Linear Feedback Shift Register) tend to have fixed structure without such flexibility. Here, fully-adaptable CRC accelerator based on a table-based algorithm is proposed. The table-based algorithm is a flexible method commonly used in software implementations. It has been rarely implemented with the hardware, since it is believed that the operational speed is not enough. However, by using pipelined structure and efficient use of memory modules in FPGAs, it appeared that the table-based fixed CRC accelerators achieved better performance than traditional implementation. Based on the implementation, fully-adaptable CRC accelerator which eliminate the need for many non-adaptable CRC implementations is proposed. The accelerator has ability to process arbitrary number of input data and generates CRC for any known CRC standard, up to 65 bits of generator polynomial, during run-time. Further, we modify Table generation algorithm in order to decrease its space complexity from O(nm) to O(n). On Xilinx Virtex 6 LX550T board, the fully-adaptable accelerators occupy between 1 to 2% area to produce maximum of 289.8 Gbps at 283.1 MHz if BRAM is deployed, or between 1.6 -14% of area for 418 Gbps at 408.9 MHz if tables are implemented in logic. Proposed architecture enables further expansion of throughput by increasing a number of input bits M processed at a time.

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A Parallel CRC Algorithm Based on Symbolic Polynomial

Zhang

2012

Advances in Intelligent and Soft Computing

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Design and Implementation of a Field Programmable CRC Circuit Architecture

Cited by 25 publications

References 10 publications

Configurable CRC Error Detection Model for Performance Analysis of Polynomial: Case Study for the 32-Bits Ethernet Protocol

Configurable CRC Error Detection Model for Performance Analysis of Polynomial: Case Study for the 32-Bits Ethernet Protocol

High-Speed Fully-Adaptable CRC Accelerators

A Parallel CRC Algorithm Based on Symbolic Polynomial

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