Design and implementation of a generic 2D orthogonal discrete wavelet transform on FPGA

Benkrid, A.; Benkrid, Khaled; Crookes, Danny

doi:10.1109/fpga.2003.1227252

Cited by 13 publications

(19 citation statements)

References 16 publications

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“…In this work we make use of a dynamically reconfigurable architecture to modify the resource allocation for the system based on the image quality required by the application. Benkrid et al [5] discuss that the overall performance and area depends significantly on the precision of intermediate bits used in the design. This motivates us to further look at bit allocation as another aspect of polymorphism in our Poly-DWT structure.…”

Section: Hardware Implementation Of Dwtmentioning

confidence: 99%

“…Much research has been done in the development of DWT architectures for image processing [4,5,17,21,29]. A good survey on architectures on DWT coding is given by [39].…”

Section: Hardware Implementation Of Dwtmentioning

confidence: 99%

“…In [12], the authors present a complete video deliver chain including a video server, negotiation and scalable video clients using a wavelet-based coding scheme at its core. Many hardware implementations have also been proposed in the research literature [2,4,5,17,20,29,43]. These implementations aim at reducing hardware complexity in order to improve the system throughput.…”

Section: Introductionmentioning

confidence: 98%

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Polymorphic Wavelet Transform

Pande

Zambreno

2013

Embedded Multimedia Security Systems

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Many modern computing applications have been enabled through the use of real-time multimedia processing. While several hardware architectures have been proposed in the research literature to support such primitives, these fail to address applications whose performance and resource requirements have a dynamic aspect. Embedded multimedia systems typically need a power and computation efficient design in addition to good compression performance. In this chapter, we introduce a Polymorphic Wavelet Architecture (Poly-DWT) as a crucial building block towards the development of embedded systems to address such challenges. We illustrate how our Poly-DWT architecture can potentially make dynamic resource allocation decisions, such as the internal bit representation and the processing kernel, according to the application requirements. We introduce a filter switching architecture that allows for dynamic switching between 5/3 and 9/7 wavelet filters and leads to a more power-efficient design. Further, a multiplier-free design with a low adder requirement demonstrates the potential of Poly-DWT for embedded systems. Through an FPGA prototype, we perform a quantitative analysis of our Poly-DWT architecture, and compare our filter to existing approaches to illustrate the area and performance benefits inherent in our approach. Poly-DWT serves as an example of joint design of algorithms and architectures for multimedia compression.

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Section: Hardware Implementation Of Dwtmentioning

confidence: 99%

“…Much research has been done in the development of DWT architectures for image processing [4,5,17,21,29]. A good survey on architectures on DWT coding is given by [39].…”

Section: Hardware Implementation Of Dwtmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

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Polymorphic Wavelet Transform

Pande

Zambreno

2013

Embedded Multimedia Security Systems

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“…Due to the wavelet's popularity over past several years there has been growing interest in implementing the discrete wavelet transform in hardware [9,10]. Much of the work on DWT involves parallel platforms to save both memory access and computation.…”

Section: Dwtmentioning

confidence: 99%

High speed and bi-mode image compression core for onboard space application

Wang

Gu²,

Chen³

2009

SPIE Proceedings

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This paper presents a bi-mode, high performance Discrete Wavelet Transform-based image compression core for future spacecrafts and micro-satellites. The hardware solution proposed here exploits an optimized CCSDS IDC algorithm and consists of a lossless mode and a lossly mode. The throughput of the core is improved 40 times using parallel architecture and pipeline technique， and a data rate of about 12.5M pixles/s can be sustained at 50MHz for the lossly mode. The experimental results indicate that this core has high performance at coding efficiency, data rate and error containment for both of the two modes.

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“…Hardware implementations such as those using ASICs or FPGAs are capable of accelerating these computations by exploiting the inherent algorithmic parallelism. DWT has been widely used for image and video coding, and many hardware implementations have been proposed in the research literature [1], [2], [3], [4], [5], [6], [7]. These implementations aim at reducing hardware complexity in order to improve system throughput.…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of efficient reconfigurable wavelet filters

Pande

Zambreno

2008

2008 IEEE International Conference on Electro/Information Technology

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Abstract-Real-time image and multimedia processing applications such as video surveillance and telemedicine can have dynamic requirements of system latency, throughput, and power consumption. In this paper we discuss the design of reconfigurable wavelet filters for image processing applications that can meet such dynamic requirements. We generate several efficient hardware designs based on a derived family of bi-orthogonal 9/7 filters. An efficient folded and multiplier-free implementation of a 9/7 filter is obtained with the help of nine adders, which is a significant improvement over other existing approaches. We also propose an architecture that allows for on-the-fly switching between 9/7 and 5/3 filter structures. A performance comparison of these filters and their hardware requirements with other existing approaches demonstrates the suitability of our choice.

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Design and implementation of a generic 2D orthogonal discrete wavelet transform on FPGA

Cited by 13 publications

References 16 publications

Polymorphic Wavelet Transform

Polymorphic Wavelet Transform

High speed and bi-mode image compression core for onboard space application

Design and analysis of efficient reconfigurable wavelet filters

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