Design and implementation of an efficient hardware integer motion estimator for an HEVC video encoder

Alcocer, Estefania; Gutierrez, R.; López-Granado, Otoniel; Malumbres, Manuel P.

doi:10.1007/s11554-016-0572-4

Cited by 22 publications

(5 citation statements)

References 14 publications

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“…Another full‐search integer ME architecture is proposed in [34], and implemented in Xilinx Virtex‐5 and Virtex‐7 FPGAs. The comparison is given in Table 3, where the frame rate with 4K‐UHD is an estimated value from Virtex‐5 operating frequency as it requires 4096 cycles neglecting initial delays, for the search range of

64 \times 64

pixels.…”

Section: Resultsmentioning

confidence: 99%

VLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video Encoding

Vayalil

Kong

2017

IET Circuits, Devices & Syst

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Motion estimation (ME) is the most computationally intensive task in video encoding. This study proposes a fullsearch variable-block-size ME for the high-efficiency video coding or H.265 specification. The proposed method reduces memory requirements to a large extent by following a Morton order for data reading and a sum of absolute differences reuse strategy. The data bandwidth demand is also diminished by broadcasting data into multiple processing elements. This ME accelerator supports variable-block-size prediction blocks ranging from 8 × 4 to 64 × 64, and is reconfigurable in various search ranges for a trade-off between performance and area. The proposed method for very-large-scale integration (VLSI) architecture is synthesized with 32 nm technology, and is capable of real-time encoding of ultra-high-definition (4K-UHD, at 30 Hz) video with a search range of 64 pixels in both horizontal and vertical directions, operating at a frequency of 282 MHz.

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64 \times 64

pixels.…”

Section: Resultsmentioning

confidence: 99%

VLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video Encoding

Vayalil

Kong

2017

IET Circuits, Devices & Syst

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“…High-Efficiency Video Coding (HEVC) or H.265 is considered the successor of the H.264 video codec for higher resolution video applications [777,778]. This new codec is doubling the compression ration of its predecessor [779][780][781]. FPGA implementations and tests of this codec started in 2012 and today has the highest ADY and PDLY (50% of the documents published in the last three years, see Figure 13).…”

Section: Compression Standardsmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

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“…Though the PE array is reconfigurable only in the horizontal dimension, the time consumed to perform ME is less compared to other architectures and hence it can support real-time encoding of UHD video at a frequency of 282 MHz. Even though the ME architecture implemented in [1] achieves high throughput compared to [40], the area overhead is huge and hence not suitable for handheld or battery operated application which requires very less power consumption. ME architecture implemented in [24] reuses the partial 4x4 SAD blocks and schedules of the PE blocks appropriately to achieve run-time optimization.…”

Section: Reconfigurable Architecture For Motion Estimationmentioning

confidence: 99%

Review on Architectures of Motion Estimation for Video Coding Standards

C¹,

Sivanantham²

2018

IJET

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Various video coding standards like H.264 and H.265 are used for video compression and decompression. These coding standards use multiple modules to perform video compression. Motion Estimation (ME) is one of the critical blocks in the video codec which requires extensive computation. Hence it is computationally complex, it critically consumes a massive amount of time to process the video data. Motion Estimation is the process which improves the compression efficiency of these coding standards by determining the minimum distortion between the current frame and the reference frame. For the past two decades, various Motion Estimation algorithms are implemented in hardware and research is still going on for realizing an optimized hardware solution for this critical module. Efficient implementation of ME in hardware is essential for high-resolution video applications such as HDTV to increase the decoding throughput and to achieve high compression ratio. A review and analysis of various hardware architectures of ME used for H.264 and H.265 coding standards is presented in this paper.

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Design and implementation of an efficient hardware integer motion estimator for an HEVC video encoder

Cited by 22 publications

References 14 publications

VLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video Encoding

VLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video Encoding

Field Programmable Gate Array Applications—A Scientometric Review

Review on Architectures of Motion Estimation for Video Coding Standards

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