Design and implementation of an improved MA‐APUF with higher uniqueness and security

Abstract

An arbiter physical unclonable function (APUF) has exponential challenge‐response pairs and is easy to implement on field‐programmable gate arrays (FPGAs). However, modeling attacks based on machine learning have become a serious threat to APUFs. Although the modeling‐attack resistance of an MA‐APUF has been improved considerably by architecture modifications, the response generation method of an MA‐APUF results in low uniqueness. In this study, we demonstrate three design problems regarding the low uniqueness that APUF‐based strong PUFs may exhibit, and we present several foundational principles to improve the uniqueness of APUF‐based strong PUFs. In particular, an improved MA‐APUF design is implemented in an FPGA and evaluated using a well‐established experimental setup. Two types of evaluation metrics are used for evaluation and comparison. Furthermore, evolution strategies, logistic regression, and K‐junta functions are used to evaluate the security of our design. The experiment results reveal that the uniqueness of our improved MA‐APUF is 81.29% (compared with that of the MA‐APUF, 13.12%), and the prediction rate is approximately 56% (compared with that of the MA‐APUF (60%‐80%).

Implementation and characterization of flash‐based hardware security primitives for cryptographic key generation

“…Various PUF systems have been presented, including ring oscillator (RO) PUF [13,14], arbiter PUF [15,16], and memory-based PUF [17][18][19]. Most types of PUFs required additional circuitry dedicated to the device, thus increasing hardware complexity, which in turn makes it difficult to apply to resource-constrained IoT devices.…”