Design and implementation of bandwidth-aware memory placement and migration policies for heterogeneous memory systems

Yu, Seongdae; Park, Seongbeom; Baek, Woongki

doi:10.1145/3079079.3079092

Cited by 20 publications

(10 citation statements)

References 24 publications

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“…Dynamic data placement has been employed to enable high performance on heterogeneous memory [2,12,22,24,46,57,58,61,76,78,79,82,86,87]. Most of those solutions are application agnostic, which means that they track page (or data) access frequency [2,12,22,24,78,79,82,87] or manage DRAM as a hardware cache for PMM [46,57,76,86] without the knowledge of data semantics. However, the data semantics gives critical indications on memory access patterns, which is useful to direct data placement and avoid unnecessary data movement.…”

Section: Dynamic Data Placement Based On Data Semanticsmentioning

confidence: 99%

“…Effectively placing data objects of an SpTCSeq in DRAM and PMM for high performance is critical to use PMM to address the memory capacity problem faced by SpTCSeq. To decide data placement on HM, the traditional solutions track page (or data) access frequency [2,12,22,24,58,61,78,79,82,87] or manage DRAM as a hardware cache for PMM [46,57,76,86], and then reactively place frequently accessed data objects into DRAM subject to the DRAM capacity constraint. However, those solutions are application-agnostic, and cause unnecessary and frequent data movement because of short-term variance in memory access patterns.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Athena

Liu

Gioiosa

et al. 2021

Proceedings of the ACM International Conference on Supercomputing

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Sparse tensor contraction sequence has been widely employed in many fields, such as chemistry and physics. However, how to efficiently implement the sequence faces multiple challenges, such as redundant computations and memory operations, massive memory consumption, and inefficient utilization of hardware. To address the above challenges, we introduce Athena, a high-performance framework for SpTC sequences. Athena introduces new data structures, leverages emerging Optane-based heterogeneous memory (HM) architecture, and adopts stage parallelism. In particular, Athena introduces shared hash table-represented sparse accumulator to eliminate unnecessary input processing and data migration; Athena uses a novel data-semantic guided dynamic migration solution to make the best use of the Optane-based HM for high performance; Athena also co-runs execution phases with different characteristics to enable high hardware utilization. Evaluating with 12 datasets, we show that Athena brings 327-7362× speedup over the state-ofthe-art SpTC algorithm. With the dynamic data placement guided by data semantics, Athena brings performance improvement on Optane-based HM over a state-of-the-art software-based data management solution, a hardware-based data management solution, and PMM-only by 1.58×, 1.82×, and 2.34× respectively. Athena also showcases its effectiveness in quantum chemistry and physics scenarios. CCS CONCEPTS• Mathematics of computing → Mathematical software performance; • Computing methodologies → Shared memory algorithms.

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Section: Dynamic Data Placement Based On Data Semanticsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Athena

Liu

Gioiosa

et al. 2021

Proceedings of the ACM International Conference on Supercomputing

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show abstract

“…Finally, a third placement policy is based on the observation that, with a pure fill DRAM first strategy, bandwidthintensive workloads might saturate DRAM bandwidth while not taking advantage of the available PM bandwidth. Hence, a bandwidth balance strategy tries to distribute hot pages across DRAM and PM, in some appropriate ratio, with the goal of maximizing the aggregate bandwidth that applications can attain when accessing different pages in parallel [60], [30].…”

Section: Dram+pm Memory Hierarchiesmentioning

confidence: 99%

Dynamic Page Placement on Real Persistent Memory Systems

Marques¹,

Kuzmin²,

Barreto³

et al. 2021

Preprint

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As persistent memory (PM) technologies emerge, hybrid memory architectures combining DRAM with PM bring the potential to provide a tiered, byte-addressable main memory of unprecedented capacity. Nearly a decade after the first proposals for these hybrid architectures, the real technology has finally reached commercial availability with Intel Optane™ DC Persistent Memory (DCPMM). This raises the challenge of designing systems that realize this potential in practice, namely through effective approaches that dynamically decide at which memory tier should pages be placed.In this paper, we are the first, to our knowledge, to systematically analyze tiered page placement on real DCPMM-based systems. To this end, we start by revisiting the assumptions of state-of-the-art proposals, and confronting them with the idiosyncrasies of today's off-the-shelf DCPMM-equipped architectures. This empirical study reveals that some of the key design choices in the literature rely on important assumptions that are not verified in present-day DRAM-DCPMM memory architectures.Based on the lessons from this study, we design and implement HyPlacer, a tool for tiered page placement in off-the-shelf Linux-based systems equipped with DRAM+DCPMM. In contrast to previous proposals, HyPlacer follows an approach guided by two main practicality principles: 1) it is tailored to the performance idiosyncrasies of off-theshelf DRAM+DCPMM systems; and 2) it can be seamlessly integrated into Linux with minimal kernel-mode components, while ensuring extensibility to other HMAs and other data placement policies. Our experimental evaluation of HyPlacer shows that it outperforms both solutions proposed in past literature and placement options that are currently available in off-the-shelf DCPMM-equipped Linux systems, reaching an improvement of up to 11x when compared to the default memory policy in Linux.

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“…In contrast to uniform-workers, BWAP takes the asymmetric BWs of every node into account to determine and enforce an optimized application-specific weighted interleaving. Our proposal is inspired by recent research for hybrid memory systems [11], [23], [43]. These works have shown that, when a CPU (or GPU [23]) is served by different memory technologies (such as NVRAM or DRAM) with differing BWs, an optimal placement is one that (proportionally) place fewer pages at the lower-BW memories.…”

mentioning

confidence: 99%

“…The same NUMA memory node may be accessible through different BWs by different threads, depending on each thread's location within the NUMA topology. This implies that optimizing page interleaving from the perspective of a given worker node (as done by the recent proposals for hybrid systems [11], [23], [43]) will not always yield the best overall performance. Instead, the optimization problem needs to consider a complex W ×N BW matrix, where W and N denote the number of worker nodes and total nodes, respectively.…”

mentioning

confidence: 99%

Bandwidth-Aware Page Placement in NUMA

Gureya¹,

Neto²,

Karimi³

et al. 2020

Preprint

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Page placement is a critical problem for memoryintensive applications running on a shared-memory multiprocessor with a non-uniform memory access (NUMA) architecture. State-of-the-art page placement mechanisms interleave pages evenly across NUMA nodes. However, this approach fails to maximize memory throughput in modern NUMA systems, characterized by asymmetric bandwidths and latencies, and sensitive to memory contention and interconnect congestion phenomena.We propose BWAP, a novel page placement mechanism based on asymmetric weighted page interleaving. BWAP combines an analytical performance model of the target NUMA system with on-line iterative tuning of page distribution for a given memory-intensive application. Our experimental evaluation with representative memory-intensive workloads shows that BWAP performs up to 66% better than state-of-the-art techniques. These gains are particularly relevant when multiple co-located applications run in disjoint partitions of a large NUMA machine or when applications do not scale up to the total number of cores.

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Design and implementation of bandwidth-aware memory placement and migration policies for heterogeneous memory systems

Cited by 20 publications

References 24 publications

Athena

Athena

Dynamic Page Placement on Real Persistent Memory Systems

Bandwidth-Aware Page Placement in NUMA

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