Design and implementation of dual port SRAM memory architecture using MOSFET's

Srinivas, Seema; Gudi, Anandthirtha B.

doi:10.1109/icspace.2017.8343457

Cited by 6 publications

(1 citation statement)

References 7 publications

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“…The ALU (Arithmetic Logic Unit) is a frequently accessed CPU module actively involved in executing most instructions [27,28]. The dedicated word ALU can perform 18 different operations, with operation codes obtained from bits 37 to 32 of the 40-bit instruction, as reported in Table 4.…”

Section: Word Alumentioning

confidence: 99%

Low-Latency FPGA-Based PLC Microprocessor for Industrial Automation in Compliance with IEC-61131-3

Cancino-Escobar,

Delgado-Del-Carpio,

Solís-Cisneros

et al. 2024

Arab J Sci Eng

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This study presents the design and implementation of a PLC microprocessor adhering to the IEC-61131-3 standard, executed on a Cyclone-V FPGA using a DE10-NANO development board. Our microprocessor optimizes the central processing unit by streamlining the data path, achieving a remarkable simulated response time of approximately 60 ns, equivalent to three clock cycles at a 50MHz frequency for Boolean operations. To substantiate our approach, we conducted practical experiments utilizing a FESTO conveyor station, employing relays as actuators, and incorporating optical and inductive sensors. The results underscore the feasibility of our proposed approach and serve as practical validation of its efficacy. This work introduces a promising avenue for the development of cost-effective PLCs employing SoC FPGA variants. Additionally, a thorough comparison of execution times with other early reported architectures. Our microprocessor outperforms even well-established PLCs like the S7-312, with substantial reductions in execution times of 94.54% for floating-point operations, 71.42% to 93.33% for word operations, and up to 78.57% for bit operations.

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Section: Word Alumentioning

confidence: 99%