Design and implementation of fast floating point units for FPGAs

Abstract

<p>Due to growth in demand for high-performance applications that require high numerical stability and accuracy, the need for floating-point FPGA has been increased. In this work, an open-source and efficient floating-point unit is implemented on a standard Xilinx Sparton-6 FPGA platform. The proposed design is described in a hierarchal way starting from functional block descriptions toward modules level design. Our implementation used minimal resources available on the targeting FPGA board, tested on Sparton-6 FPGA platform and verified on ModelSim. The open-source framework can be embedded or customized for low-cost FPGA devices that do not offer floating-point units.</p>

Comparative study of single precision floating point division using different computational algorithms

“…Booth-based multiplication is used to pre-calculate the carry and the presented design improved the speed and dissipated less power with respect to the existing multipliers [27]. A fast-floating point unit is designed and implemented for FPGAs [28]. As floating-point number is separated into three parts where a fixed number of bits is used to represent these three parts that are sign, exponent and mantissa.…”