Design and Implementation of Floating Point Divide-Add Fused Architecture

Pande, Kuldeep; Jaykar, Shashant; Peshattiwar, Atish

doi:10.1109/csnt.2015.179

Cited by 6 publications

(2 citation statements)

References 9 publications

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“…In digital signal processing application encryption and decryption algorithms in cryptography; a divider is one of the most important hardware blocks which is applicable in most applications [18] and also in various mathematical computational algorithms used to design floating-point divide-add fused (DAF) architecture [19]. The floating-point DAF architecture has a dedicated unit for floating point division followed by addition or subtraction so that a combined operation is performed [20]. The delay time and better device utilization which is an important factor and have to optimize are done by a division architecture based on the Vedic mathematics algorithm Parvartya sutra [21].…”

Section: Introductionmentioning

confidence: 99%

Comparative study of single precision floating point division using different computational algorithms

Singh¹,

Parihar²

2023

IJRES

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<span>This paper presents different computational algorithms to implement single precision floating point division on field programmable gate arrays (FPGA). Fast division computation algorithms can apply to all division cases by which an efficient result will be obtained in terms of delay time and power consumption. 24-bit Vedic multiplication (Urdhva-Triyakbhyam-sutra) technique enhances the computational speed of the mantissa module and this module is used to design a 32-bit floating point multiplier which is the crucial feature of this proposed design, which yields a higher computational speed and reduced delay time. The proposed design of floating-point divider using fast computational algorithms synthesized using Verilog hardware description language has a 32-bit floating point multiplier module unit and a 32-bit floating point subtractor module unit. Xilinx Spartan 6 SP605 evaluation platform is used to verify this proposed design on FPGA. Synthesis results provide the device utilization and propagation delay parameters for the proposed design and a comparative study is done with previous work. Input to the divider is provided in IEEE 754 32-bit formats.</span>

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Section: Introductionmentioning

confidence: 99%

Comparative study of single precision floating point division using different computational algorithms

Singh¹,

Parihar²

2023

IJRES

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“…Though adder(subtractor) and multiplier circuits have been studied and crafted into highly efficient arithmetic units with high performance and low cost, the design of divider circuits has attracted much less research due to lower usage than adders and multipliers [70] and due to the more complicated and difficult operations involved. Due to its complexity, divider is often a performance limiting module in many applications such as digital signal processors (DSPs) [71], [72]. This is also the case for other systems where real-time processing is required, especially in graphics and video processing [73].…”

Section: Implementations For Arithmetic Divisionsmentioning

confidence: 99%

High throughput VLSI architecture for gradient guided filter with approximated arithmetic operations

Wu¹

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Guided image filtering has been applied widely for increasing demand of high performance filtering, especially for real-time image/video processing. Gradient guided filter improves the filtering quality, reducing the halo-artifacts problem due to its edge-aware characteristics. However, the gradient guided filter algorithm has high computation complexity and the computation involves global pixels, which hinder its VLSI implementation for real-time full-HD application. This work addresses these issues and a VLSI architecture is proposed for the gradient guided image filter. Several design techniques are developed and used in the design to achieve high computation speed and high throughput. A seamless dataflow is proposed for the complete system that consists of three main processing stages, specifically the preprocessing stage, the linear coefficient computation stage and the output stage.The preprocessing stage applies a down-sampling technique with a large sampling rate to reduce computation cost in terms of circuit size, processing time and power consumption. The global parameter values are quickly derived with reasonable good global information maintained so that the quality of the filtering results are not sacrificed when these values are applied in the subsequent two stages.The linear coefficient computation stage contains the most complex computations such as square root, division and exponential function. Down-sampling technique is applied with a sampling rate lower than in the preprocessing stage so as to balance the computation cost and filtering accuracy. In addition, the intensive arithmetic computation modules that dominate the critical path delay are redesigned by using adequate approximated operations. Specifically, novel non-iterative dividers are developed to replace original dividers for reducing delays in the critical paths. With the proposed non-iterative division, ii the quotient of the division is modeled as a normalized curved surface. The curved surface is partitioned into small regions and approximated by smaller planes for efficient hardware implementation. Curve fitting method and mixed integer linear programming method are adopted and evaluated for local optimization of the approximation errors. In this way, the dividers are implemented with only simple arithmetic operations and a small look-up table. As a result, the operation is fast and the approximation errors are optimized while satisfying the accuracy requirement. The other intensive computation, the exponentiation function, is also simplified by piecewise linear approximation, and implemented with only shifters and adder trees. As such, the approximated computations are used to improve the computation performance and simplify the designs of the complex arithmetic modules.The output stage employs parallel processing and operates at a frequency 16 times higher to restore the filtering results to its original full frame size. The linear coefficients obtained from the downsampling stage are applied concurrently to all the 16 pixels i...

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Design and synthesis of goldschmidt algorithm based floating point divider on FPGA

Singh

Sasamal

2016

2016 International Conference on Communication and Signal Processing (ICCSP)

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Design and Implementation of Floating Point Divide-Add Fused Architecture

Cited by 6 publications

References 9 publications

Comparative study of single precision floating point division using different computational algorithms

Comparative study of single precision floating point division using different computational algorithms

High throughput VLSI architecture for gradient guided filter with approximated arithmetic operations

Design and synthesis of goldschmidt algorithm based floating point divider on FPGA

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