Design and implementation of fourth arm for elimination of bearing current in NPC-MLI fed Induction motor drive

Bharatiraja, C.; Munda, Josiah L.; Raghu, S.; Chelliah, Thanga Raj; Tariq, Mohd

doi:10.1109/pedes.2016.7914557

Cited by 6 publications

(6 citation statements)

References 25 publications

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“…Due to this simplicity in modified SVM strategy, the proposed drive is switched at 900 Hz. It is low switching frequency as compared to the reported IMD in the literature [21–23]. Due to this low switching frequency, proposed IMD has less switching losses and higher efficiency.…”

Section: Introductionmentioning

confidence: 94%

Multi‐pulse AC–DC converter fed SVM controlled NPC inverter based VCIMD

Kant

Singh

2018

IET Power Electronics

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A multi-pulse AC-DC converter fed space vector modulation (SVM) controlled neutral point clamped (NPC) inverter based vector control induction motor drive (VCIMD) is proposed here for medium power rating applications. To improve the power quality at supply side, a 12-pulse AC-DC converter is used and to meet the IEEE-519 standard, a high-pass filter is also used along with it. A three-level NPC inverter is utilised on the motor side to enhance the required performances of an induction motor drive (IMD). A modified SVM strategy is proposed to balance the capacitor voltages of the NPC inverter and to switch this inverter at very low switching frequency. The neutral point voltage balancing is achieved by the time adjustment between positive and negative small vectors. The model of proposed IMD is developed using the Simulink/MATLAB platform, and simulated response is validated with test results on a developed prototype in the laboratory to demonstrate its usefulness for medium power applications.

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Section: Introductionmentioning

confidence: 94%

Multi‐pulse AC–DC converter fed SVM controlled NPC inverter based VCIMD

Kant

Singh

2018

IET Power Electronics

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“…The complete elimination of CM issues is a big challenge in PWM based drives. Henceforth, the combination of passive methods such as CM choke, and CM EMI filters along with constant CMV PWM techniques are use in the practice for the complete elimination of CMV affects 12‐14 . The two‐level six switch PWM inverters have the advantages of size and low cost, and therefore attract more consideration in most of industrial drives.…”

Section: Introductionmentioning

confidence: 99%

A hybrid space vector modulation for the near‐zero common‐mode voltage and common‐mode current mitigation in diode‐clamped multilevel‐inverter‐fed induction motor drive

Selvaperumal

Kirubakaran

Bharatiraja

2020

Int Trans Electr Energ Syst

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Three-level diode-clamped (DC) multilevel inverters (MLIs) and its pulse width modulations (PWMs) are studied widely due to its extensive rewards in industrial drives. These modulation schemes are mainly concentrated to mitigate the zero common-mode (CM) voltage (CMV) and CM current (CMC). Unfortunately, although achieving near-zero CMV, these conventional methods are inadequate to maintain the DC-link low-frequency neutral point voltage oscillations. Hence, bulky DC-link capacitors are used in DC-MLIs. In this article, a full CM voltage eliminated the modified space vector modulation (SVM) method by combining the three medium switching vectors (M 3 V) with one zero vector and two medium switching vectors (M 2 ZV) is proposed. The hybridization of M 3 V + M 2 ZV uses the simple digital circuit to combine M 3 V and M 2 ZV, which creates near-zero CMV and CMC with an improved DC-link capacitor voltage balancing. The studies on the creation and effects of CMV and CMC are presented in detailed. Compared with the early reported full CMV elimination research works, the proposed method maintains the DC-link capacitors voltage balancing without compromising the complete elimination of the CMV. Depending on the reference vector modulation indices and DClink capacitor voltages, the proposed method uses the mixture of both the M 3 V and M 2 ZV switching states. The nominated switching vectors keep the CMV and CMC near to zero with capacitor voltage fluctuation with 1.8%. List of Symbols and Abbreviations: C b , bearing capacitance; C rs , rotor to stator frame parasitic capacitance; C wf , parasitic capacitive; C wr , parasitic capacitance between stator and rotor winding; C ws , parasitic capacitance in stator winding and frame; E SW , switching energy matrix; f o , fundamental frequency; f s , switching frequency; i b , bearing current; M a , modulations index; P sw , switching losses; S f , switching function; T s , switching time; V ao , V bo , and V co , inverter a, b, and c pole voltages; V b , bearing voltage; V C1 and V C2 , DC-link capacitors; V CM , common-mode voltage; V DC , DC-link

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“…The side effects induced by CMV have been frequently reported in practical operation. For instance, the CMV may cause common‐mode electromagnetic interference (EMI) emissions of converters [5], as well as bearing failure and insulation failure of motors [6]. Therefore, the effects of CMV should be investigated in practical application.…”

Section: Introductionmentioning

confidence: 99%

“…The CMV also can be suppressed by improving hardware topology of inverter system [5,6,13–16]. In Ref.…”

Section: Introductionmentioning

confidence: 99%

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H14 Three‐Level Inverter for Common‐Mode Voltage Suppression

Wang³

et al. 2020

IEEJ Transactions Elec Engng

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This paper presents an H14 three-level inverter topology and the corresponding control method for common-mode voltage (CMV) suppression based on the three phase three-level neutral-point-clamped inverter. Operation performance of the proposed H14 three-level inverter is first analyzed under different switching patterns, and the corresponding CMV under each operation states is investigated. The control method of H14 inverter is presented by following a feasible minimal CMV output within the switching patterns, and the switching function is given which is very easy to be implemented. Furthermore, the operation performances of the proposed H14 inverter in terms of total harmonic distortion of output current, DC link neutral-point voltage oscillation and CMV are investigated in simulation and hardware-in-the-loop experiment. The verification results show that the proposed H14 three-level inverter is able to suppress the CMV, the maximum amplitude of CMV is reduced from V dc /3 to V dc /6 especially with desirable operation performances of inverter.

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Design and implementation of fourth arm for elimination of bearing current in NPC-MLI fed Induction motor drive

Cited by 6 publications

References 25 publications

Multi‐pulse AC–DC converter fed SVM controlled NPC inverter based VCIMD

Multi‐pulse AC–DC converter fed SVM controlled NPC inverter based VCIMD

A hybrid space vector modulation for the near‐zero common‐mode voltage and common‐mode current mitigation in diode‐clamped multilevel‐inverter‐fed induction motor drive

H14 Three‐Level Inverter for Common‐Mode Voltage Suppression

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