Design and Implementation of High-Performance ECC Processor with Unified Point Addition on Twisted Edwards Curve

Abstract

With the swift evolution of wireless technologies, the demand for the Internet of Things (IoT) security is rising immensely. Elliptic curve cryptography (ECC) provides an attractive solution to fulfill this demand. In recent years, Edwards curves have gained widespread acceptance in digital signatures and ECC due to their faster group operations and higher resistance against side-channel attacks (SCAs) than that of the Weierstrass form of elliptic curves. In this paper, we propose a high-speed, low-area, simple power analysis (SPA)-resistant field-programmable gate array (FPGA) implementation of ECC processor with unified point addition on a twisted Edwards curve, namely Edwards25519. Efficient hardware architectures for modular multiplication, modular inversion, unified point addition, and elliptic curve point multiplication (ECPM) are proposed. To reduce the computational complexity of ECPM, the ECPM scheme is designed in projective coordinates instead of affine coordinates. The proposed ECC processor performs 256-bit point multiplication over a prime field in 198,715 clock cycles and takes 1.9 ms with a throughput of 134.5 kbps, occupying only 6543 slices on Xilinx Virtex-7 FPGA platform. It supports high-speed public-key generation using fewer hardware resources without compromising the security level, which is a challenging requirement for IoT security.

Analysis of Efficient Implementation of Elliptic Curve Cryptography Architecture for Resource Constraint Application

“…It offers area-efficient hardware architecture for digital signature verification with its reconfigurable platform implementation. [4] Due to high resistance to SCAs and simplicity, the Edwards curve is gaining enormous interest among security researchers [23]. ECPM is quicker and more stable on Edwards curves than on elliptical curves in the Weierstrass form [24].…”

“…To perform ECPM, distinct hardware architectures for PA and PD are not necessary. Moreover, through rendering the secret key identical to power tracing, the unified PA prevents possible SPA attacks [4]. Implementing the Twisted Edward curve can use the unified formula for both doubling and addition, thereby implementing side-channel security [26][27].…”

“…RNS based work presented in [5] and [28] over GF (2 256 ) on Virtex-7 achieves a low latency output. Unified Point Addition on twisted Edwards Curve was implemented on GF (2 256 ) and Virtex 7 platform in [4] by achieving low latency. A lightweight ECC accelerator was implemented in [16].…”

“…To execute high-speed modular multiplication, an efficient radix-4 interleaved modular multiplier was proposed. It is well suited for resource-constrained IoT devices because of its less hardware resource requirements and high computation speed [4]. The performance parameter like clock frequency, latency, no.…”

“…ECC requires a shorter key length than RSA to provide the same level of security. This smaller key size feature makes ECC the best suited for resource-constrained IoT devices as well as high-speed cryptographic processors [4]. ECC offers strong security per bit and provides an efficient hardware implementation in terms of power consumption and speed than other PKC algorithms [5].…”