Design and Implementation of Low power FinFET based Compressor

Nagaraju, V.; Babu, P. Ashok; Sadgurbabu, B.; Vallabhuni, Rajeev Ratna

doi:10.1109/icspc51351.2021.9451693

Cited by 9 publications

(7 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These filters provide the linear model, inverse model of the unknown system and predict the present value of the random signal. [16][17][18][19][20][21][22][23][24][25] They can be designed as FIR or IIR filters. The adaptive FIR is more preferred because of its stability and easy updating of the filter coefficients.…”

Section: Introductionmentioning

confidence: 99%

Digital Filter based Adder Module Realization High-Speed Switching Functions

2023

VLSI

View full text Add to dashboard Cite

FIR filter bank play a vital role in any signal processing systems. The FIR filter is used to implement any frequency response digitally. Usually, the FIR filters contain multipliers, adders and many delays. As we know, the number of MAC operations (multiply and accumulate) makes the FIR filter less efficient and increases hardware complexity. So in this project, we included DA (Distributed Arithmetic) architecture in designing the efficient adaptive FIR filter. The pipelined Distributive Arithmetic architecture provides less power, less area and high values of throughput in creating an adaptive FIR filter. These are used in Echo cancellations, Radio channel equalizers and speech coding. DA architecture also helps in improving the processing speed of the FIR filter by eliminating the number of multipliers. A reconfigurable filter design can be achieved with the help of this Distributive Arithmetic architecture. Here the sum of the partial products which is pipelined is passed as the input values, and it is stored in the LUT (lookup tables) of the distributive architecture. By replacing the adder of the shift accumulation unit with a carry-save adder, the area of the proposed design is reduced. By placing the ripple carry adder, the size and delay are reduced to a further extent. Here we will use the Xilinx ISE tool to verify the simulation result, area required and time consumed.

show abstract

Section: Introductionmentioning

confidence: 99%

Digital Filter based Adder Module Realization High-Speed Switching Functions

2023

VLSI

View full text Add to dashboard Cite

show abstract

“…In order to design high order IIR filter, filter stages of all pass filter, the delays and the masking filter methods. [15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32] The frequency components of the input signals is allowed by the all pass filter which does not have any attenuation and the all pass filter will also provide different frequency of predictive phase shifts of the input signal. All Pass Filters are also named as Delay Equalizers or Phase Correctors.…”

Section: Introductionmentioning

confidence: 99%

“…[33][34][35][36][37][38][39] For example we can get the IIR Filter which is of high pass from the Low Pass IIR Filter. [18], [40] elays and the masking filter methods [15]- [32]. uency components of the input signals is allowed by the all pass filter not have any attenuation and the all pass filter will also provide different of predictive phase shifts of the input signal.…”

Section: Introductionmentioning

confidence: 99%

FPGA based Digital Filter Design for faster operations

2023

VLSI

View full text Add to dashboard Cite

The reduced complexity design of the IIR filter is discussed in this paper. The use of the IIR filter has been variably increasing during the present times and they are realtime applications. The filter complexity reduction is done to increase the usage of filters in FPGA. In this method, the coefficients are expressed in the form of 1's and 0's. The multiplied delays have been used which is used to scale down the complexity. Signal Flow Graph plays a critical role in identifying the difficult path. IIR Filter is programmed on basis of the Synchronous Data Flow and Pipelining. The Half Band IIR filters are used for high-performance applications. This design is processed to implement in FPGA which will result in higher speed and the cost will be variably decreased as well as the consumption of power. The entire process is implemented by using the Verilog language which reduces the complication and speeds up the whole process.

show abstract

“…For many high-performance applications FPGA's internal logic has become first option because of flexibility in structure and reconfigurability and in addition to that development in technology and science also helping this out. [17][18][19][20] 740MHz is the max speed limit of computation of Xilinx Virtex-7. Filter's implementation structure is improved to attain more than 1GHz sample rate by usage of serial methods.…”

Section: Introductionmentioning

confidence: 99%

FPGA Application: Realization of IIR filter based Architecture

2023

VLSI

View full text Add to dashboard Cite

This document investigation is performed on improved implementation of an Infinite Impulse Response (IIR) filter which can utilized practically. There are many other proposed models for IIR filters that yield promising and efficient results. The suggested IIR filter model known as a parallel-pipeline based on FIR filter. FIR filters on the other hand provide linear phase response, high stability, and limited precision errors. So, FIR based IIR filter offers better efficiency than its previous models. Moreover, there are other techniques such as the Two-Level Pipeline based IIR filter model and look-ahead-based model are mentioned and discussed. And the synthesis and results are obtained on a Xilinx Virtex-5 field-programmable Gate Array Board. After analyzing all design models mentioned, A new model for the implementation IIR filter is discussed which increases the efficiency of the filter.

show abstract

Design and Implementation of Low power FinFET based Compressor

Cited by 9 publications

References 21 publications

Digital Filter based Adder Module Realization High-Speed Switching Functions

Digital Filter based Adder Module Realization High-Speed Switching Functions

FPGA based Digital Filter Design for faster operations

FPGA Application: Realization of IIR filter based Architecture

Contact Info

Product

Resources

About