Design and Implementation of Low-Pass, High-Pass and Band-Pass Finite Impulse Response (FIR) Filters Using FPGA

Kolawole, Emmanuel S.; Ali, Warsame H.; Cofie, Penrose; Fuller, John; Tolliver, C.; Obiomon, Pamela

doi:10.4236/cs.2015.62004

Cited by 18 publications

(5 citation statements)

References 4 publications

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“…In this case we use 34 of 4656 logic slices, not even 1% of the chip: this shows how effective and less resource usage is been achieve when implemented with FPGA. Below are some other benefits of using FPGA in this Stepper Motor implementation [11]. 1) Performance-The hardware parallelism nature of FPGAs exceed the computing power of digital signal processors (DSPs) by breaking the paradigm of sequential execution and accomplishing more per clock cycle .…”

Section: Resultsmentioning

confidence: 99%

Rapid Prototype with Field Gate (A Design and Implementation of Stepper Motor Using FPGA)

Ali¹,

Kolawole²,

Obiomon³

et al. 2016

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This paper presents the design and implementation of a Stepper Motor using Nexys2 circuit board based on a Xilinx Spartan 3E Field Programmable Gate Array (FPGA) device with VHDL code. The algorithm implemented on FPGA allows a substantial decrease of the equivalent processing time developed by different velocity controllers. The Stepper Speed control is achieved using VHDL code, and the hardware digital circuit is designed for a programmable rotational stepper motor using VHDL as a tool and FPGA as a target technology. The 50 MHZ provided by the starter kit is divided to obtain the necessary delay time between the motor phases that ranges between 2-10 m seconds. Though output selections, the direction of rotation of the stepper motor besides the magnitude of the angle of movement and the rotation speed can be controlled. The major advantage of using reconfigurable hardware (FPGA) in implementing the Stepper Motor instead of a discrete digital component is that it makes modifications to the design easy and quick and also, the total design hence represents an embedded system (works without computer). The total programmable hardware design that controlled on the stepper motor movement, occupied an area that did not exceed 12% of the chip resources.

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Section: Resultsmentioning

confidence: 99%

Rapid Prototype with Field Gate (A Design and Implementation of Stepper Motor Using FPGA)

Ali¹,

Kolawole²,

Obiomon³

et al. 2016

Self Cite

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show abstract

“…In paper [11] design and implementation of low pass, high pass and band pass fir filter using Spartan -6 FPGA device. The EDA tool is used to define filter order and coefficients, FIR filter is used for simulink simulation.…”

Section: Iii-literature Surveymentioning

confidence: 99%

Novel Architecture of Fir Lattice Filter with Reduced Interconnect Delay Impacts Towards Reduced Power-delay Product using Pipelining and Parallel Processing for Medical Applications

2023

IJFMR

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Three important parameters area, speed and power are important. In VLSI design, the speed is determined by the critical path delay. Delay is depending on the data path taken for processing in the VLSI design. By minimizing data-path delay using efficient architecture the speed of the design of system can be improved in turn to result in better performance. In this new era, data-path delay is the dominating one compared to logic delay. So, it is very essential to concentrate more towards path delay in any architecture design. Even though the speed is important it is having in trade of with power. This data-path delay can be reduced by different technique like pipelining, parallel processing, register retiming. Also, by constructing this architecture in an innovative way the power is having trade of with delay. So the power-delay product can be taken as the reduced one. In this paper, various architecture of delay-product optimized FIR filter and Lattice filter architecture is being surveyed and implemented in order to get minimum delay-power product

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“…(e-mail: Vidyasaraswathi bit-bangalore.edu.in) @ @ @ Akarsha Yadav, Vijaya Prakash, and Vidya Saraswathi Design of Modified RNS-PPA Based FIR Filter for High-Speed Application process, a normal number or integer is broken down into small modules using a modulo set. For example, the moduli set is (7|8|9) and the inputs (X, Y) is equal to (10,15) respectively. Then the inputs X and Y are divided by these three co-prime numbers (7|8|9) and the result obtained was X1= (3|2|1), Y1= (1|7|6), where X1, Y1 are the RNS from a representation of input signals (X, Y).…”

Section: B Forward Conversionmentioning

confidence: 99%

Design of Modified RNS-PPA Based FIR Filter for High-Speed Application

Yadav

Prakash²,

Saraswathi³

2022

EJENG

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The primary motive of this paper is to give the design and implementation of RNS (Residue Number System) based Area efficient and excessive-overall performance FIR filter of 4-tap, eight-tap, 16-tap of input eight bit. Additionally, RNS mathematics is a treasured device for theoretical research of the limits of fast mathematics. These proposed strategies additionally have a few additions operation, through the use of convention adder will decrease the speed of operation and additionally increase the number of logic gates. So, to conquer the one's issues we are using Ladner Fischer parallel prefix adder to lower the delay and area. First, the multiplier is designed through the use of RNS approach. In which the delay is decreased through 78.57% and power dissipation is likewise reduced to 64.65% for the RNS_PPA multiplier. A combination of those algorithms generates a brand-new structure of excessive speed and low implementation area in a single multiplier for FIR filter using Xilinx 14.7.

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Design and Implementation of Low-Pass, High-Pass and Band-Pass Finite Impulse Response (FIR) Filters Using FPGA

Cited by 18 publications

References 4 publications

Rapid Prototype with Field Gate (A Design and Implementation of Stepper Motor Using FPGA)

Rapid Prototype with Field Gate (A Design and Implementation of Stepper Motor Using FPGA)

Novel Architecture of Fir Lattice Filter with Reduced Interconnect Delay Impacts Towards Reduced Power-delay Product using Pipelining and Parallel Processing for Medical Applications

Design of Modified RNS-PPA Based FIR Filter for High-Speed Application

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