Design and Implementation of Real-Time Image Acquisition Chip Based on Triple-Hybrid Encryption System

Abstract

With the improved hardware storage capabilities and the rapid development of artificial intelligence image recognition technology, information is becoming image-oriented. Increasingly sensitive image data needs to be processed. When facing a large amount of real-time sensitive image data encryption and decryption, ensuring both the speed and the security is an urgent demand. This paper proposes an original triple-hybrid encryption system for a real-time sensitive image acquisition chip. This encryption system optimizes the symmetric encryption algorithm AES, asymmetric encryption algorithm ECC, and chip authentication algorithm PUF in pursuit of security, calculation speed, and to ensure that it is lightweight. The three optimized algorithms are further mixed and reused on the circuit level, to ensure mutual protection while making full use of their advantages. Apart from sensitive image protection at the algorithm level, the image chip itself is also protected by an innovative PUF chip authentication method that prevents it from being tampered with and copied. Triple-hybrid encryption system hardware implementation achieves a frequency of 132.5 MHz under the Virtex-5 FPGA with an area of 2834 Slices; with Virtex-7 FPGA, it reaches a frequency of 137.6 MHz with an area of 2716 Slices. The system is also implemented on SMIC 40 nm ASIC, and the clock frequency reaches 480 MHz and the area is 94,812.4 μm2. In terms of computing speed, the peak image encryption speed is 6.15 Gb/s, which meets the real-time image encryption requirement. In terms of hardware resource usage, AES reduced the hardware area by 60.1% compared with the results in other literature, ECC reduced the hardware area by 43.4%, and the PUF hardware area decreased exponentially with the increase in information entropy. The implementation of the three algorithms is reasonable and cost-effective, and the mixture of algorithms does not increase the required capacity of the hardware resource. The triple-hybrid encryption system cooperates with the image acquisition subsystem, storage subsystem, and asynchronous clock subsystem through software control to realize a complete triple-hybrid encryption SoC chip solution, and was successfully taped-out under the SMIC 40 nm process with all constraints passed and a total area of 10.59 mm2.

Performance Comparison of Symmetric and Asymmetric Encryption Algorithms

“…Asimetrik kripto sistemlerinden biri olan ve temeli Diffie -Hellman (DH) anahtar değişimine dayanan El Gamal algoritması; Taher Elgamal [23] tarafından önerilmiştir. Ayrık logaritma problemleri önerisi, imzalama yapısı ve şifreleme algoritmasından oluşan şablonuyla çoğu kriptografik yöntemlerin esinlenilen durumunda konumlanmıştır [24,25].…”

Design and Implementation of Low-Power IoT RISC-V Processor with Hybrid Encryption Accelerator

“…Li et al proposed an original triple-hybrid encryption system for a real-time sensitive image acquisition chip. This encryption system optimizes the symmetric encryption algorithm AES, asymmetric encryption algorithm ECC, and chip authentication algorithm PUF in pursuit of security; AES reduced the hardware area by 60.1%, and ECC reduced the hardware area by 43.4% [15]. However, prevailing hybrid encryption systems often rely on conventional processor architectures, with their acceleration units mostly attached to the CPU's bus as peripherals, failing to fully exploit the flexibility and scalability inherent in the RISC-V instruction set.…”