Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso

Banu, Sufia; Gupta, Shweta

doi:10.37391/ijeer.100246

Cited by 11 publications

(3 citation statements)

References 19 publications

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“…(S/H) sample and hold device is then passed to an eight input OR gate, which produces the digital output from the discrete input. The static power reduction of 6T SRAM cell that employs power gating transistors having only PMOS, NMOS and combination of PMOS and NMOS power gating transistor is described [29] that reduces to power signi cantly.…”

Section: Proposed Technique (Input Leakage Controlled Stack Transisto...mentioning

confidence: 99%

A New Circuit‑Level Leakage Power Reduction Technique of Static Logic Gates for Analog to Digital Converter in CMOS Technology using Virtuoso

Banu,

Gupta

2023

Preprint

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The total power in a device is composed of three basic components, having dynamic power due to switching activity, static power while the device in sleep mode and short circuit power while a short amount of current flows from power supply rail (VDD) to ground terminal (GND). The dynamic power component in a CMOS circuit is dominating at lower technology nodes. With scaling, having lesser than 65nm regime the leakage power increases than dynamic power that becomes challenging for the VLSI design engineers. This paper describes a new circuit level leakage power reduction technique called as Input Leakage Controlled Stack Transistor-ILCST for CMOS circuits at circuit level that is been used in 4-bit flash Analog to Digital Converter applicable for deep brain neurostimulator. Analog to Digital Converters (ADC) are crucial for transforming analogue signals from the real world into digital data in the form of 0 and 1. Flash is the most popular ADC owing to its fast speed nature. In this study, a 4-bit flash ADC with a, sample and hold (S/H), comparators and a priority encoder are designed and simulated. To perform sampling process, the sample and hold circuit is utilized. An encoder is a necessary component of a Flash ADC. It converts the comparator output-generated thermometer code (TC) into binary code (BC). The speed, area, and power must all be taken into account while designing the flash analogue to digital converter. Work is implemented using 45nm technology node and carried the simulations in Cadence Virtuoso tool. The static power is reduced significantly using the proposed technique.

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Section: Proposed Technique (Input Leakage Controlled Stack Transisto...mentioning

confidence: 99%

A New Circuit‑Level Leakage Power Reduction Technique of Static Logic Gates for Analog to Digital Converter in CMOS Technology using Virtuoso

Banu,

Gupta

2023

Preprint

Self Cite

View full text Add to dashboard Cite

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“…It could also be used to fix multiple bit defects when the memory is protected with a more robust algorithm that can identify multiple bit faults. M. Karimzadeh-Farshbafan et al, [9] propounds a new programming problem for reliability-aware service placement that considers both the primary and backup servers at the same time. Researchers analyse a multi-infrastructure (multi-InP) provider scenario in which each InP provides the Network Operator (NO) with servers that are stable.…”

Section: ░ 1 Introductionmentioning

confidence: 99%

Low-Power VLSI Implementation of Novel Hybrid Adaptive Variable-Rate and Recursive Systematic Convolutional Encoder for Resource Constrained Wireless Communication Systems

Ramanna

Ganesan

2022

IJEER

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In the modern wireless communication system, digital technology has tremendous growth, and all the communication channels are slowly moving towards digital form. Wireless communication has to provide the reliable and efficient transfer of information between transmitter and receiver over a wireless channel. The channel coding technique is the best practical approach to delivering reliable communication for the end-users. Many conventional encoder and decoder units are used as error detection and correction codes in the digital communication system to overcome the multiple transient errors. The proposed convolutional encoder consists of both Recursive Systematic Convolutional (RSC) Encoder and Adaptive Variable-Rate Convolutional (AVRC) encoder. Adaptive Variable-Rate Convolutional encoder improves the bit error rate performance and is more suitable for a power-constrained wireless system to transfer the data. Recursive Systematic Convolutional encoder also reduces the bit error rate and improves the throughput by employing the trellis termination strategy. Here, AVRC encoder ultimately acquires the channel state information and feeds the data into a fixed rate convolutional encoder and rate adaptor followed by a buffer device. A hybrid encoder combines the AVRC encoder and RSC encoder output serially and parallel, producing the solid encoded data for the modulator in the communication system. A modified turbo code is also obtained by placing interleaver between the two encoder units and building the stronger code word for the system. Finally, the conventional encoder system is compared and analyzed with the proposed method regarding the number of LUT’s, gates, clock cycle, slices, area, power, bit error rate, and throughput.

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“…Figure 5: Categorization of FinFET Configurations3.1 Shorted Gate FinFET (SG-FinFET) and independent gate FinFET (IG-FinFET)The FinFETs are categorized into two types based on the gate structure such as SG-FinFET and IG-FinFET as illustrated in figure6. The SG-FinFET and IG-FinFET are often recognized as 3-terminal (3T) and four-terminal (4T) devices[31] [1]. The rear and front gates of SG FinFETs are both physically shorted, whereas the gates of IG FinFETs are physically isolated[45].…”

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confidence: 99%

A Comparative Analysis of FinFET Based SRAM Design

Kumbar¹,

Waje²

2022

IJEER

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FinFETs are widely used as efficient alternatives to the single gate general transistor in technology scaling because of their narrow channel characteristic. The width quantization of the FinFET devices helps to reduce the design flexibility of Static Random Access Memory (SRAM) and tackles the design divergence between stable, write and read operations. SRAM is widely used in many medical applications due to its low power consumption but traditional 6T SRAM has short channel effect problems. Recently, to overcome these problems various 7T, 9T, 12T, and 14T SRAM architectures are designed using FinFET. This article provides a comprehensive survey of various designs of SRAM using FinFET. It offers a comparative analysis of FinFET technology, power consumption, propagation delay, power delay product, read and write margin. Additionally, the article presents the simulation of the 5T and 6T SRAM design using CMOS and FinFET for 14 nm technology using Microwind 3.8 simulation tool. The outcomes of the proposed SRAM design are compared with several recent designs based on power, delay, and, and various stability analysis parameters such as read, write and hold noise margin. Finally, the article discusses the challenges in SRAM design using FinFET and provides the future direction for optimization of accuracy, area, speed, delay, and cost of the FinFET-based SRAMs.

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Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso

Cited by 11 publications

References 19 publications

A New Circuit‑Level Leakage Power Reduction Technique of Static Logic Gates for Analog to Digital Converter in CMOS Technology using Virtuoso

A New Circuit‑Level Leakage Power Reduction Technique of Static Logic Gates for Analog to Digital Converter in CMOS Technology using Virtuoso

Low-Power VLSI Implementation of Novel Hybrid Adaptive Variable-Rate and Recursive Systematic Convolutional Encoder for Resource Constrained Wireless Communication Systems

A Comparative Analysis of FinFET Based SRAM Design

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