Design and microarchitecture of the IBM System z10 microprocessor

Abstract

The IBM System z10e microprocessor is currently the fastest running 64-bit CISC (complex instruction set computer) microprocessor. This microprocessor operates at 4.4 GHz and provides up to two times performance improvement compared with its predecessor, the System z9t microprocessor. In addition to its ultrahigh-frequency pipeline, the z10e microprocessor offers such performance enhancements as a sophisticated branch-prediction structure, a large second-level private cache, a data-prefetch engine, and a hardwired decimal floating-point arithmetic unit. The z10 microprocessor also implements new architectural features that allow better software optimization across compiled applications. These features include new instructions that help shorten the code path lengths and new facilities for software-directed cache management and the use of 1-MB virtual pages. The innovative microarchitecture of the z10 microprocessor and notable differences from its predecessors and the IBM POWER6e microprocessor are discussed.

The cache and memory subsystems of the IBM POWER8 processor

“…Starting with the POWER4 processor [12] and z10* [13] processors, the IBM I/O subsystem was built upon a proprietary ecosystem of I/O chips [14] attached to IBM's proprietary GX bus and later GX+ and GX++ buses to achieve higher I/O throughput than possible with the standardized interfaces available at the time. Different break-out I/O hub chips provided connectivity to PCI-X**, PCIe devices, and InfiniBand** or Ethernet fabrics.…”

IBM zEnterprise 196 microprocessor and cache subsystem

“…Figure 4 shows the pipeline stages of the z196 processor from the first decode stage (D1) to completion. In the prior z10 microprocessor pipeline design [2], the fixed-point unit (FXU) execution stage is placed after the cache data return stage of the LSU; hence, there is no need to stall the execution of an FXU instruction if it is dependent on a load data event. However, this caused results of the RR-type instructions 1 to go through many nonrequired stages (e.g., LSU pipe stages A0-A3), delaying the availability of results and eventually delaying the branch resolution cycle.…”

“…Together, these features enable the platform to better support the traditional Large Systems Performance Reference (LSPR) workload set, to better utilize the hardware/software synergy that emerged on the preceding z10 platform, and to provide a highly competitive platform for emerging workloads while continuing the trend for increased box capacity within a constant energy footprint from one generation to the next. The sections that follow contain a comparative analysis between the z196 platform and its predecessor z10 platform [2,3].…”

IBM z13 firmware innovations for simultaneous multithreading and I/O virtualization

“…Over several generations of the IBM z Systems, more parallelism has been achieved by adding processor cores, and by increasing instruction-level parallelism [1,2]. Multiple threads, capable of running independent instruction streams on one processor core, increase parallelism even further.…”