IBM zEnterprise 196 microprocessor and cache subsystem

Abstract

The IBM zEnterprise A 196 (z196) system, announced in the second quarter of 2010, is the latest generation of the IBM System z A mainframe. The system is designed with a new microprocessor and memory subsystems, which distinguishes it from its z10 A predecessor. The system has up to 40% improvement in performance for traditional z/OS A workloads and carries up to 60% more capacity when compared with its z10 predecessor. The memory subsystem has four levels of cache hierarchy (L1 through L4) and constructs the L3 and L4 caches with embedded DRAM silicon technology, which achieves approximately three times the cache density over traditional static RAM technology. The microprocessor has 50% more decode and dispatch bandwidth when compared with the z10 microprocessor, as well as an out-of-order design that can issue and execute up to five instructions every single cycle. The microprocessor has an advanced branch prediction structure and employs enhanced store queue management algorithms. At the date of product announcement, the microprocessor was the fastest complex-instruction-set computing processor in the industry, running at a sustained 5.2 GHz, executing approximately 1,100 instructions, 220 of which are cracked into reduced-instruction-set computing-type operations, to achieve large performance gains in legacy online transaction processing and compute-intensive workloads.

Transactional Memory Architecture and Implementation for IBM System Z

“…The transactional execution facility is first implemented in the IBM zEC12 processor [1], the successor of the z196 processor described in [20]. The processor can decode 3 instructions per clock cycle; simple instructions are dispatched as single micro-ops, and more complex instructions are cracked into multiple micro-ops.…”

The IBM z13 multithreaded microprocessor

“…These pipes are split into two groups of three decoding pipes each. Some of the complex z/Architecture instructions are decomposed (or cracked) into two or three micro-operations or micro-ops [3] and each micro-op is decoded by one of these six pipes. More complex z/Architecture instructions are expanded into two or more groups (for example the z/Architecture load multiple instruction).…”

“…This mainframe microprocessor design has evolved in multiple dimensions, including frequency, pipeline depth, branch prediction, superscalar/instruction level parallelism, out-of-order execution, and multithreading. The z13 builds upon the out-of-order execution base introduced on the IBM zEnterprise* 196 (z196) [2,3], and its performance gains are achieved relative to that design and its successorVthe IBM zEC12 system [4]Vin both single-thread (single code stream) and in total system-level throughput. The single-thread performance gains are predominately achieved by major advancements in branch prediction throughput; higher instruction decode, dispatch, and completion rates; larger fixed point and floating point execution bandwidth; larger caches; and larger out-of-order execution windows.…”

The IBM z13 processor cache subsystem

“…The complex has a four-level cache hierarchy, comprising L1, L2, L3, and L4 caches [7], connecting to a shared-distributed memory interface, and externally connected via a multitude of I/O channels.…”