Design and Modelling of Silicon Quantum Dot Based Single Qubit Spin Quantum Gates

Bhat, Hilal Ahmad; Malik, Gul Faroz A.; Khanday, Farooq Ahmad

doi:10.1007/s10773-022-05239-y

Cited by 3 publications

References 22 publications

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Optimization and performance investigation of 1-Toffoli gate quantum full adders for spin-torque-based n-qubit architecture

Kulkarni,

Haghparast,

Kaushik

2023

Opt Quant Electron

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Quantum computing (QC) is suitable for reversible computing due to its inherent parallel processing ability and fast speed. It also helps to address the issue of high-power dissipation in classical computing. Moreover, QC gates are the sequence of elementary operations such as single-qubit rotation and two-qubit entanglement. Elementary quantum operations are required to be reduced for the realization of complex computing. In this paper, optimization of 1-Toffoli gate-based quantum full adders (QFAs) in terms of the number of elementary operations with the help of quantum library {Ry, Rz, $$\sqrt{\mathrm{SWAP}}$$ SWAP } is carried out. Moreover, the performance of two different 1-Toffoli QFAs is investigated in terms of execution time, fidelity, and number of electrons required to realize the QFAs. Improvement in fidelity is 0.7% and 0.57% for QFA1 and QFA2, respectively, compared to the fidelity of 2-Toffoli QFA. A 9.97% increase in execution time is mandatory for the QFA2 compared to QFA1. The QFA2 takes 5% more number of electrons in comparison to QFA1.

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Optimization and performance investigation of 1-Toffoli gate quantum full adders for spin-torque-based n-qubit architecture

Kulkarni,

Haghparast,

Kaushik

2023

Opt Quant Electron

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CNTFET and RRAM Based Low Power Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits

Khurshid,

Singh

2023

J CIRCUIT SYST COMP

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The advent of multi-valued logic (MVL) systems provides considerable improvements in energy consumption and computational efficiency compared to binary logic systems. Using resistive random-access memory (RRAM) and carbon nanotube field effect transistors (CNTFETs), this manuscript presents a new design method for ternary logic gates (standard ternary inverter (STI), ternary NOR, and ternary NAND) and some arithmetic circuit applications are implemented based on the proposed ternary logic gates. The simulations of the proposed circuits are carried out in Synopsis HSPICE software by employing 32-nm Stanford CNTFET technology along with the Stanford RRAM model. The robustness of the designed CNTFET-RRAM STI circuit is investigated for variations in process parameters. Simulation results verify that the proposed designs outperform other CNTFET based ternary logic circuits in terms of number of components, power consumption, delay and power delay product (PDP). Furthermore, a reduced change is perceived with respect to power consumption and PDP of the presented logic gates with process deviation, and variations in supply voltage, temperature, capacitance and frequency. The presented STI, TNAND, TNOR, ternary half adder (THA) and ternary multiplier (TMUL) circuits exhibit an improvement in PDP with less transistor count as compared to the other existing designs in the literature.

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Optimal Circuit Decomposition of Reversible Quantum Gates on IBM Quantum Computers

Bhat

Khanday

Shah

2023

Advances in Systems Analysis, Software Engineering, and High Performance Computing

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A critical task in utilizing quantum physics in many application fields is circuit design using reversible quantum gates. Using decomposition techniques enables transformation of unitary matrices into fundamental quantum gates. Any 3x3 reversible quantum gate can be decomposed into single-qubit rotation gates and two qubit CNOT gates. In this chapter, quantum implementations of FRSG1, URG, JTF1 and R gates into CNOT gates and single qubit U3 gates with different optimization levels on a platform provided by IBM have been discussed. FRSG1 and JTF1 gates are important in applications like Stochastic computing, fingerprint authentication system, and parity generation circuits. URG gate is better in terms of number of complex functions and can be utilized to design quantum comparator circuits. R gate plays an important role in inverting and duplicating a signal. In FRSG1, URG, JTF1 and R gates, the implementation count of single qubit gates decreases by 56%, 11%, 71%, and 62%, respectively and the count of two qubit gates reduces by 15%, 26%, 41%, and 5% respectively after optimization.

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Design and Modelling of Silicon Quantum Dot Based Single Qubit Spin Quantum Gates

Cited by 3 publications

References 22 publications

Optimization and performance investigation of 1-Toffoli gate quantum full adders for spin-torque-based n-qubit architecture

Optimization and performance investigation of 1-Toffoli gate quantum full adders for spin-torque-based n-qubit architecture

CNTFET and RRAM Based Low Power Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits

Optimal Circuit Decomposition of Reversible Quantum Gates on IBM Quantum Computers

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