Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time Systems

Dridi, Mourad; Rubini, Stéphane; Lallali, Mounir; Florez, Martha Johanna Sepulveda; Singhoff, Frank; Diguet, Jean-Philippe

doi:10.1145/3264818

Cited by 7 publications

(6 citation statements)

References 39 publications

(47 reference statements)

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“…NoCs can handle dataflows that use both packet and circuit communications protocols. They are also well suited to handle mixed criticality flows [ 118 ] jointly with OS (criticality of tasks), for example safety tasks cannot be superseded or slowed down by other tasks. As previously suggested, multiple processing architecture models should co-exist within an embedded HPC system in order to meet expected processing demands of multiple applications running simultaneously.…”

Section: Addressing the Computational Gap For High Levels Of Autonmentioning

confidence: 99%

Embedded Computation Architectures for Autonomy in Unmanned Aircraft Systems (UAS)

Mejias

Diguet²,

Dezan

et al. 2021

Sensors

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This paper addresses the challenge of embedded computing resources required by future autonomous Unmanned Aircraft Systems (UAS). Based on an analysis of the required onboard functions that will lead to higher levels of autonomy, we look at most common UAS tasks to first propose a classification of UAS tasks considering categories such as flight, navigation, safety, mission and executing entities such as human, offline machine, embedded system. We then analyse how a given combination of tasks can lead to higher levels of autonomy by defining an autonomy level. We link UAS applications, the tasks required by those applications, the autonomy level and the implications on computing resources to achieve that autonomy level. We provide insights on how to define a given autonomy level for a given application based on a number of tasks. Our study relies on the state-of-the-art hardware and software implementations of the most common tasks currently used by UAS, also expected tasks according to the nature of their future missions. We conclude that current computing architectures are unlikely to meet the autonomy requirements of future UAS. Our proposed approach is based on dynamically reconfigurable hardware that offers benefits in computational performance and energy usage. We believe that UAS designers must now consider the embedded system as a masterpiece of the system.

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Section: Addressing the Computational Gap For High Levels Of Autonmentioning

confidence: 99%

Embedded Computation Architectures for Autonomy in Unmanned Aircraft Systems (UAS)

Mejias

Diguet²,

Dezan

et al. 2021

Sensors

Self Cite

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“…Wormhole switching minimizes the communication time and it does not require large capacity buffers. But, we also consider SAF switching mode because it decreases the potential congestion over the network [18].…”

Section: Supported Noc Architecturesmentioning

confidence: 99%

“…For SAF NoC, using virtual channel allows us to avoid indirect interference. With a Wormhole NoC, we need to use a virtual channel for each communication flow in order to also prevent such an interference [18]. Next, we demonstrate how those assumptions avoid indirect interference.…”

Section: Supported Noc Architecturesmentioning

confidence: 99%

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ECTM: A network-on-chip communication model to combine task and message schedulability analysis

Dridi¹,

Singhoff²,

Rubini³

et al. 2021

Journal of Systems Architecture

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“…In Reference 49, microarchitecture of a single cycle router employing bypass paths, is presented. In Reference 50, the authors propose a hybrid NoC router that uses both wormhole (for low‐critical flows) and store‐and‐forward switching techniques for high‐critical flows. The studies of References 51‐53 are other router designs that effectively control congestion and balance the network load.…”

Section: Related Workmentioning

confidence: 99%

A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

Alaei

Yazdanpanah

2020

Concurrency and Computation

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High performance system-on-chip (SoCs) designs have led to high-density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network-on-chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high-performance FPGA-based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low-power NoC router with high performance in terms of energy-efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA-based NoC with mesh topology. Performance evaluations include network-level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures. K E Y W O R D S FPGA, low-power design, multicrossbar, network-on-chip, priority-based router 1 INTRODUCTION In high-density emerging SoC architectures, there are a large number of processing elements (PEs) communicating through intensive on-chip interconnections that significantly affect different aspects of the performance. For large SoCs, point-to-point and bus-based interconnections do not provide efficient on-chip network infrastructures because of large amount of hardware, high latency, high power consumption, and/or complicated synchronization. NoCs, as high-performance architectures, arise to overcome the limitations of traditional on-chip structures. 1-5 NoCs provide high-performance and power scalable and modular interconnections. In addition, with NoC architectures, the system complexity is reduced by separating communication and computation units. A NoC includes routers, links, and network interfaces in order to prepare a network infrastructure for interconnecting PEs. Links of NoCs consist of physical channels (i.e., a group of wires), and optional virtual channels (VCs) as a set of additional buffers in routers. 4-7 The channel bit-width (the number of wires in a unidirectional channel) depends on the bandwidth requirements of the applications and available chip area. Generally, links of NoC have two physical unidirectional channels for fully duplexed communication, allowing data to flow both ways without collisions. 1 Routers are the most important modules of the communication backbone of NoC architectures. So, it is essential to design them with low latency, low power consumption, and high throughput. The router complexity and performance impacts the latency, power consumption, area, throughput, and the cost of on-chip networks. 8 Field programmable gate arrays (FPGAs) are flexible, easy-to-use, and cost effective reprogrammable devices with fast and simple design flow. FPGA designers generally do not need to care for clock distribut...

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Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time Systems

Cited by 7 publications

References 39 publications

Embedded Computation Architectures for Autonomy in Unmanned Aircraft Systems (UAS)

Embedded Computation Architectures for Autonomy in Unmanned Aircraft Systems (UAS)

ECTM: A network-on-chip communication model to combine task and message schedulability analysis

A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

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