Design and Optimization of Dual Material Gate Junctionless FinFET Using Dimensional Effect, Gate Oxide and Workfunction Engineering at 7 nm Technology Node

Kusuma, Rambabu; Talari, V. K. Hanumantha Rao

doi:10.1007/s12633-022-01769-6

Cited by 8 publications

(6 citation statements)

References 31 publications

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“…But here, with a unique HSS structure, we have minimized the fringing field effect where the edges are filled with a High-K gate oxide material. Figure 6 describes the change in the drain current for different Fin heights where we can still see the enhancement of the off current, which is minimum compared to the reported reading of Kusuma et al [23]. It can also be observed that the device minimized the effects to reduce the leakage current with the proposed device structure, and this device also increases the controllability over the channel by increasing the interface charge with the GOS structure.…”

Section: Fin Height Variationmentioning

confidence: 65%

“…The reference number along with the source is indicated in the table 3 where, Figure indicates the figure and T represents the table. Figure 11 shows the subthreshold performance of the proposed device with Kusuma et al [23] for different gate oxide combinations where the proposed HSS device enhances the SS value due to high electrostatic control over the substrate.…”

Section: Performance Comparison Of Dmg Over Smgmentioning

confidence: 99%

“…In the miniaturization process, the channel size is cut down, which decreases the distance between the source and drain and effectively reduces the performance of the device by encountering the SCEs. To avoid these issues, spacers are introduced between the two potential terminals of the device, which allow downscaling of the device to a sub-10 nm regime [5,6,[20][21][22][23]. Sreenivasulu et al [6], further enhanced the device performance by combining the High-K spacer to minimize the series resistance of the substrate and enhance the drain current.…”

Section: Introductionmentioning

confidence: 99%

“…Sreenivasulu et al [6], further enhanced the device performance by combining the High-K spacer to minimize the series resistance of the substrate and enhance the drain current. Many researchers are come up with different structures to improve the performance of FinFET with multi-fin, circular fins with different smaller radius to increase the drain current by driving the higher drain current and wider conducting channel [23][24][25][26][27][28][29][30][31].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Design of high-K dielectric HSS-DMG Junctionless FinFET using hetero GOS for nanoscale application

Kumar,

Lorenzo

2024

Eng. Res. Express

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This article presents a detailed investigation of the High-K dielectric horizontal stack spacer (HSS) dual material gate junction-less FinFET device for analog and RF application using the gate oxide stack (GOS) approach. At first, the impact of the horizontal stack spacer (HSS) with different high-K spacer materials are investigated by placing different dielectric material like HfO2, SiO2, Si3N4, and TiO2 on the horizontal spacer. The simulation results of the device indicate that the High-K dielectric HSS makes the device high stability toward the leakage current and static power dissipation at the sub-nano scale regime. The DC characteristics of the device are also investigated alongside the AC/RF characteristics. The proposed device predominantly improves performance in terms of parameters like subthreshold swing, Ion/Ioff, and DIBL. The proposed device shows a high ON current of 8.56×10 -5(A), which is about 15% higher than the existing literature, and the device also makes a notable impact on the leakage current by restricting it to 9.635×10-12. The simulation of the device is carried out with optimization of the doping to investigate and improve the device's performance. The device shows an excellent improvement in performance which is highly suitable for future-ready device applications.

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Section: Fin Height Variationmentioning

confidence: 65%

Section: Performance Comparison Of Dmg Over Smgmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design of high-K dielectric HSS-DMG Junctionless FinFET using hetero GOS for nanoscale application

Kumar,

Lorenzo

2024

Eng. Res. Express

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“…In many system-on-chip applications, FinFETs started to outperform planar MOSFETs in terms of size, efficiency, and power. 17,18 However, to continue scaling with FinFET, thinner fins are inevitable to maintain good electrostatics. Further, incorporating thinner fins reduces carrier mobility and exacerbates the threshold voltage roll-off.…”

mentioning

confidence: 99%

Gate Stack Analysis of Nanosheet FET for Analog and Digital Circuit Applications

Kumari,

Vijayvargiya,

Upadhyay

et al. 2023

ECS J. Solid State Sci. Technol.

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This manuscript demonstrates the performance comparison of vertically stacked nanosheet FET with various high-k materials in gate stack (GS) configuration. As the high-k dielectric materials are inevitable to continual scaling, in this paper, various high-k dielectric materials such as Si3N4, Al2O3 and HfO2 are incorporated in the GS, and the performance is studied. Further, DC and Analog/RF performance metrics are discussed in detail, and it is noticed that by using HfO2 in high-k GS, the on current (I ON) is enhanced by 46.7% and off current (I OFF) is decreased by 81.6% as compared to conventional NSFET (C-NSFET) without high-k GS. Also, the switching ratio (I ON/I OFF) is increased by 8× from SiO2 to HfO2, ensuring good logic applications. Moreover, compared to the C-NSFET, GS-NSFET with HfO2 offers better values for analog metrics like transconductance (gm) and transconductance generation factor (TGF). However, as the k value increases, the capacitances are also observed to be increased. As a result, the intrinsic delay (τ) increases by 9%, 6% and 20% from SiO2 to Si3N4, Si3N4 to Al2O3, Al2O3 to HfO2, respectively. On top of that, the circuit level demonstration is also performed for resistive load based inverter and ring oscillator (RO) for both C-NSFET GS NSFET with HfO2 as GS material. From circuit analysis, it is observed that by using the GS, the performance of the inverter is increased in terms of noise margins and DC gain. However, the oscillation frequency (f OSC) of 3-stage RO is decreased by 14.7% with the incorporation of GS owing to the increment in gate capacitance (Cgg). Consequently, the results will give deep insights into the performance analysis of NSFET with various high-k materials in gate stack at both device and circuit levels.

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Performance investigation of junction-less (JL) high-K vertical stack oxide (VSO) Ga2O3-FinFET for RF and linear applications

Vijaya,

Lorenzo

2024

Microsyst Technol

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Design and Optimization of Dual Material Gate Junctionless FinFET Using Dimensional Effect, Gate Oxide and Workfunction Engineering at 7 nm Technology Node

Cited by 8 publications

References 31 publications

Design of high-K dielectric HSS-DMG Junctionless FinFET using hetero GOS for nanoscale application

Design of high-K dielectric HSS-DMG Junctionless FinFET using hetero GOS for nanoscale application

Gate Stack Analysis of Nanosheet FET for Analog and Digital Circuit Applications

Performance investigation of junction-less (JL) high-K vertical stack oxide (VSO) Ga2O3-FinFET for RF and linear applications

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