2016
DOI: 10.1016/j.microrel.2016.02.001
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Design and optimization of LDMOS-SCR devices with improved ESD protection performance

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Cited by 7 publications
(1 citation statement)
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“…Lee found that a P+ strip inserted into drain region can improve the ESD failure threshold of embedded SCR LDMOS device [11]. Some other novel structures and their performance were studied for different application purposes in [12][13][14][15][16].…”
Section: Introductionmentioning
confidence: 99%
“…Lee found that a P+ strip inserted into drain region can improve the ESD failure threshold of embedded SCR LDMOS device [11]. Some other novel structures and their performance were studied for different application purposes in [12][13][14][15][16].…”
Section: Introductionmentioning
confidence: 99%