Design and optimization of MOS Current-Mode Logic circuits

Abdulkarim, Osman

doi:10.22215/etd/2007-07761

Cited by 2 publications

(3 citation statements)

References 14 publications

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“…The MCML NAND gate is the universal MCML logic gate [10,13] in Figure 3.21, by where CLK is connected to ~A, CLK ̅̅̅̅̅ to A, CLK delayed ̅̅̅̅̅̅̅̅̅̅̅̅̅̅ is connected to B and CLKdelayed is connected to ~B. MN5 in the universal gate improves the symmetry between both branches and the performance in high-speed applications.…”

Section: Differential Delay Chain Sub-block Implementationmentioning

confidence: 99%

“…Figure 3.21 shows the modified MCML NAND gate with transistor sizing done. To calculate the PMOS load size and tail NMOS size along with the biasing circuity, a complicated analysis on MCML delay model in terms of the bias current, the voltage swing and process-dependent parameters, is needed [10,13]. This goes beyond the scope of this thesis and would not be included here.…”

Section: Differential Delay Chain Sub-block Implementationmentioning

confidence: 99%

“…13 Full schematic of the linear transconductor used for current source biasing P_BiasVout, the gate voltage at TP3 shown inFigure 4.13, is the voltage used for the PMOS source current control voltage in the integrator. And additionally, it is also used in the current summing circuitry which generates the NMOS tail current sink bias voltage for the integrator also.…”

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Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz

Yu¹

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Design, Analysis and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz Run Bin YuThe clock signal is considered as the "heartbeat" of a digital system yet jitter which is a variation on the arrival time of the clock edge, could undermine the overall performance or even cause failures on the system. Deterministic jitter could be reduced during the designing process however random jitter during operation is somehow less-controllable and unavoidable. Being able to remove jitter on the clock would therefore play a vital role in system performance improvement.This thesis implements a 1GHz fully feedforward jitter reduction circuit (JRC) which can be used as an on-chip IP core at clock tree terminals to provide a low jitter clock signal to a local clock network or be used at the clock insertion point to reduce jitter from an off chip signal. It can also be stand-alone and used on PCB designs to reduce jitter on the high-frequency clock signal used on the board. This jitter attenuation circuit is implemented using IBM CMHV7SF 180nm MOSFET process, demonstrates a jitter reduction of at least 8dB at 1GHz with 33ps rms Gaussian random jitter (for a 200ps peak-to-peak randomly changing rising edge input signal).

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Section: Differential Delay Chain Sub-block Implementationmentioning

confidence: 99%

Section: Differential Delay Chain Sub-block Implementationmentioning

confidence: 99%

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