Design and optimization of multi-level TAM architectures for hierarchical SOCs

Iyengar, V.; Chakrabarty, Krishnendu; Krasniewski, Mark D.; Kumar, G. Naveen

doi:10.1109/vtest.2003.1197667

Cited by 15 publications

(32 citation statements)

References 21 publications

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“…In comparison, only a limited amount of work has been done on wrapper design and TAM optimization for SoCs with hierarchical cores. Recently in [28], [29], and [30], techniques for wrapper/TAM optimization for hierarchical SoCs have been explored. In [28], an existing hierarchyoblivious TAM optimization approach is used to iteratively solve the problem of TAM optimization for hierarchical SoCs.…”

Section: Related Prior Workmentioning

confidence: 99%

“…Recently in [28], [29], and [30], techniques for wrapper/TAM optimization for hierarchical SoCs have been explored. In [28], an existing hierarchyoblivious TAM optimization approach is used to iteratively solve the problem of TAM optimization for hierarchical SoCs. However, in this approach, the constraints related to simultaneous testing of parent and child cores are ignored.…”

Section: Related Prior Workmentioning

confidence: 99%

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Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling

Goel

Marinissen

Sehgal

et al. 2009

IEEE Trans. Comput.

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Abstract-Many system-on-chip (SoC) integrated circuits today contain multiple hierarchy levels for both design and test. Hierarchy imposes constraints on the manner in which tests must be applied to "parent" cores and their "child" cores. However, most prior work on wrapper design, test access mechanism (TAM) optimization, and test scheduling is hierarchy oblivious, i.e., these techniques treat all cores in an SoC as if they are at the same level of hierarchy. We first show that the test architecture, consisting of wrappers and TAMs, and the corresponding test schedule designed for nonhierarchical SoCs are not valid for SoCs with hierarchical cores. Next, we present two approaches for efficient testing of SoCs with hierarchical cores. In the first approach, the problem is solved by extending a conventional wrapper design; this approach leaves full flexibility for TAM optimization and test scheduling. The second approach is based on a modified wrapper design for parent cores that operates in two disjoint modes for testing of parent and child cores. This approach has an impact on the test architecture and corresponding schedule. We show how an existing test architecture design algorithm can be adapted for use with both approaches. Experiments with the ITC'02 SoC Test Benchmarks show that the first approach offers lower test application times, while the second approach incurs less area costs.

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Section: Related Prior Workmentioning

confidence: 99%

Section: Related Prior Workmentioning

confidence: 99%

Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling

Goel

Marinissen

Sehgal

et al. 2009

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…In comparison, only a limited amount of work has been done on wrapper design and TAM optimization for hierarchical SOCs. Recently in [8], the issue of wrapper design for hierarchical cores has been addressed, and in [9,12,13], wrapper design and TAM optimization techniques for hierarchical cores have been explored.…”

Section: Limitations Of Prior Workmentioning

confidence: 99%

“…In [12], a wrapper/TAM optimization approach is presented, which uses an existing hierarchy-oblivious TAM optimization approach iteratively to solve the problem of TAM optimization for hierarchical SOCs. However, in this approach, the constraint of child and parent INTEST testing being time multiplexed is ignored.…”

Section: Wrapper/tam Optimizationmentioning

confidence: 99%

“…Hence, in the INTEST P mode, the available TAM wires are distributed between the parent core scan chains and wrapper cells, as well as the child core TAM architecture. This was ignored in the prior work on TAM optimization for hierarchical cores in [12]. In the INTEST C mode, child core internal testing is carried out; all child cores are in INTEST mode.…”

Section: Wrapper/tam Optimizationmentioning

confidence: 99%

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