Design and performance analysis of phase frequency detector for high speed application

Dhiman, Archna; Sharma, Tripti; Kaur, Bobbinpreet

doi:10.1109/icisc.2018.8399057

Cited by 6 publications

(2 citation statements)

References 17 publications

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“…This makes the transistor to turn on faster therefore increasing the speed of the circuit. But this will lead to increase in the leakage current in the transistors during its static stage thereby leading to leakage power consumption [2]. The PFD circuit taken here is the one where there is no reset path.…”

Section: Methodsmentioning

confidence: 99%

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Low Power Phase Frequency Detector for PLL

2023

IRJMETS

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One of the difficulties in achieving high performance in VLSI design today has been the development of low power consumption requirements for the various applications and electronic products. As a result, many technologies have been developed to reduce power consumption, and one of them is the sleep transistor technique. In this paper, we compare two different phase frequency detector circuits for phase locked loop with sleep transistor technique. The phase frequency detector is implemented in cadence virtuoso using the library GPDK090 of 90 nm CMOS Technology. It is observed that, by applying the power optimization technique there is reduction in power consumption thereby seeing an improvement of 29%.

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Section: Methodsmentioning

confidence: 99%

“…They get the input frequency from a crystal oscillator, usually in the MHz range, and generate the system frequency in the GHz range. This should match the output frequency with the reference frequency [2].…”

Section: Introductionmentioning

confidence: 99%