Design and performance analysis of a low complexity digital clock recovery algorithm for software-defined radio applications

Montazeri, Ali; Kiasaleh, Kamran

doi:10.1109/tce.2010.5606256

Cited by 7 publications

(11 citation statements)

References 16 publications

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“…The implementation of some parallel challenging SDR blocks like symbol synchronization on an FPGA can significantly reduce the performance requirements on a personal computer. The analysis of the resource utilization by authors in [14] and [15] for their symbol timing system confirmed too that more than one quarter of dedicated multipliers is necessary for RTL synthesis on FPGA. The presented synchronization system was compared with a conventional synchronization system, where a Farrow structure [11] is used to implement the time-varying fractional delay, FIR filter.…”

Section: Fpga Synthesismentioning

confidence: 91%

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Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

Fiala¹,

Linhart²

2015

RADIOENGINEERING

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This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed.

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Section: Fpga Synthesismentioning

confidence: 91%

“…General division in (14) has to be eliminated for fast fixed-point implementation and optimal VHDL synthesis on the FPGA. We can recognize that 1/N T I /T s [11].…”

Section: Interpolation Control Blockmentioning

confidence: 99%

Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

Fiala¹,

Linhart²

2015

RADIOENGINEERING

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“…The benefit of removing these frequency components in this manner is that no bandpass filter (or PLL) is required, which reduces the cost of implementing this estimator. In previous implementations of SL algorithms that use an integrator and a band-pass filter [10], [11], the output of the integrator before and after a dump was shown to be significantly different, leading to discontinuity in the signal. This discontinuity was shown to impact the recovered clock signal after band-pass filter operation.…”

Section: Methodsmentioning

confidence: 99%

“…When making a noise-tolerant implementation of an SL-based algorithm, more resources are required for averaging as the targeted noise level increases. The averaging processes included in SL algorithms remove a significant level of unwanted harmonics using one of the following: a phaselocked loop (PLL) [1], a narrowband-pass filter [1], or a combination of an integrator and a relaxed shape band-pass filter Manuscript [10], [11]. Here, we use only a customized integrator to remove the most disruptive harmonics.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Spectral-Line Clock Recovery Algorithm for SDR Applications

Montazeri

Webb

Kiasaleh

2011

IEEE Trans. Circuits Syst. II

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In this brief, we present a low-complexity digital spectral-line (SL) clock recovery algorithm that is suitable for low-power software-defined radio (SDR) communications. In order to reduce the resource and power consumption, we used a customized integrator to remove the most disruptive SL harmonics. Performance is established in terms of mean-square timing error (MSTE), computational complexity, and power consumption. To assess the viability of the proposed algorithm, the MSTE of the proposed method is compared to that of a typical SL clock recovery algorithm. Furthermore, using a field-programmable gate array platform, we address the computational complexity of the proposed algorithm for implementation in SDR applications. We show that the MSTE for the proposed method is almost the same as that for typical SL clock recovery algorithms while requiring significantly less resources and power.

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“…The authors in [17] have evaluated the variance of jitter in SLN synchroniser, stating that this estimator has the best performance over other feedforward algorithms. Several blind estimators are introduced and evaluated in [18, 19]. In [20–24] the timing estimators are used in digital coherent optical receivers.…”

Section: Introductionmentioning

confidence: 99%