Design and Performance Analysis of Ultra-Low Voltage Rail-to-Rail Comparator in 130 nm CMOS Technology

Nagy, Lukáš; Arbet, Daniel; Kovac, Martin; Potocny, Miroslav; Stopjaková, Viera

doi:10.1109/ddecs.2018.00016

Cited by 6 publications

(3 citation statements)

References 9 publications

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“…This test can be considered quite strict, since it would also reveal issues with the input offset voltage. Monte-Carlo simulations performed on 3000 samples in corner and ambient temperatures resulted in the mean value of input offset V offset = 592 uV with standard deviation of σ = 1.91 mV [15]. Furthermore, the power consumption at V DD = 0.4 V has been measured in the upper half of nW range including the ESD structures leakage, PCB, and oscilloscope probe parasitics.…”

Section: Evaluation Of the Proposed LV Circuitsmentioning

confidence: 99%

Ultra-Low-Voltage IC Design Methods

Arbet¹,

Nagy²,

Stopjaková³

2020

Integrated Circuits/Microchips

Self Cite

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The emerging nanoscale technologies inherently offer transistors working with low voltage levels and are optimized for low-power operation. However, these technologies lack quality electronic components vital for reliable analog and/or mixed-signal design (e.g., resistor, capacitor, etc.) as they are predominantly used in high-performance digital designs. Moreover, the voltage headroom, ESD properties, the maximum current densities, parasitic effects, process fluctuations, aging effects, and many other parameters are superior in verified-by-time CMOS processes using planar transistors. This is the main reason, why low-voltage, low-power high-performance analog and mixed-signal circuits are still being designed in mature process nodes. In the proposed chapter, we bring an overview of main challenges and design techniques effectively applicable for ultra-low-voltage and low-power analog integrated circuits in nanoscale technologies. New design challenges and limitations linked with a low value of the supply voltage, the process fluctuation, device mismatch, and other effects are discussed. In the later part of the chapter, conventional and unconventional design techniques (bulk-driven approach, floating-gate, dynamic threshold, etc.) to design analog integrated circuits towards ultra-low-voltage systems and applications are described. Examples of ultra-low-voltage analog ICs blocks (an operational amplifier, a voltage comparator, a charge pump, etc.) designed in a standard CMOS technology using the unconventional design approach are presented.

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Section: Evaluation Of the Proposed LV Circuitsmentioning

confidence: 99%

Ultra-Low-Voltage IC Design Methods

Arbet¹,

Nagy²,

Stopjaková³

2020

Integrated Circuits/Microchips

Self Cite

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“…After this, the currents are both mirrored and summed up at the node N1, before the data is reinstituted and reshaped by the last-stage shaping buffer. A simple rail-to-rail comparator [20,21], as shown in Figure 5, was constructed as a composite of P and NMOS pairs. The amplifier with rail-to-rail input identifies the voltage difference from the input data (OP and ON) and converts them into currents through the input trans-conductor cell (M1-M4).…”

Section: Receivermentioning

confidence: 99%

A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

et al. 2019

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This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 ps@2.5 Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

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“…The offset voltage expression for dynamic comparator implementation is validated in 40nm and 0.25-mum CMOS technology. An ultra low-voltage non-clocked voltage comparator in standard twin-well 130 nm CMOS is analyzed by Nagy et al [9]. The operating temperature was -20-85 °C with the power supply voltage of 0.6 Chin et al [10] designed a low power comparator working at high frequency with low supply voltage of 1V.…”

Section: Introductionmentioning

confidence: 99%

Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application

Yedukondalu¹,

Arunachalam²,

Bolisetty

et al. 2022

IJEECS

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when compared with Fin Field-Effect Transistor (FinFET) device. The leakage current is more in CMOS devices while in FinFET device due to the control of multi-Gates on the channel, the leakage current is reduced. This will improve the power consumption in the FinFET device when compared to CMOS devices. The comparator results shows that CMOS device is inferior when compared with FinFET device comparator. For the implementation of the comparator Spice model were used in this work. The software used in the project is synopsis Hspice.

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Design and Performance Analysis of Ultra-Low Voltage Rail-to-Rail Comparator in 130 nm CMOS Technology

Cited by 6 publications

References 9 publications

Ultra-Low-Voltage IC Design Methods

Ultra-Low-Voltage IC Design Methods

A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application

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