2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER) 2016
DOI: 10.1109/discover.2016.7806237
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Design and performance comparison of adiabatic 8-bit multipliers

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Cited by 10 publications
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“…The conventional Wallace Tree diagram is shown in the Figure 6 and the proposed Wallace tree diagram, with above simplified key components, is demonstrated in Figure 7. Compared with the conventional Wallace tree [50], three stages are reduced to two stages in our work, which means fewer transistors and less area is used. Further, the speed of the whole multiplier is enhanced.…”
Section: Proposed Wallace Treementioning
confidence: 99%
“…The conventional Wallace Tree diagram is shown in the Figure 6 and the proposed Wallace tree diagram, with above simplified key components, is demonstrated in Figure 7. Compared with the conventional Wallace tree [50], three stages are reduced to two stages in our work, which means fewer transistors and less area is used. Further, the speed of the whole multiplier is enhanced.…”
Section: Proposed Wallace Treementioning
confidence: 99%
“…Wallace Dadda and Vedic Dadda multiplier have been implemented using ECRL (Efficient Charge Recovery Logic) adiabatic design and achieved 77% less power compared to conventional CMOS [2] . An array multiplier has been implemented using CEPAL (Complementary Energy Path Adiabatic Logic) in 32nm HSPICE tool and 47% reduction in power consumption was achieved [3] .…”
Section: State Of the Artmentioning
confidence: 99%