Design and performance evaluation of virtual-channel based NoC

Hou, Ning; Zhang, Duoli; Du, Guotong; Song, Yong; Wen, Haihua

doi:10.1109/icasid.2009.5276901

Cited by 5 publications

References 7 publications

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A performance enhanced dual-switch Network-on-Chip architecture

Zeng

Watanabe

2015

The 20th Asia and South Pacific Design Automation Conference

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Network-on-Chip (NoC) is an attractive solution for future systems on chip (SoC). The network performance depends critically on the performance of packets routing. However, as the network becomes more congested, packets will be blocked more frequently. It would result in degrading the network performance. In this article, we propose an innovative dual-switch allocation (DSA) design. By introducing two switch allocations, we can make utmost use of idle output ports. Experimental results show that our design significantly achieves the performance improvement in terms of throughput and latency at the cost of very little power overhead.

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A performance enhanced dual-switch Network-on-Chip architecture

Zeng

Watanabe

2015

The 20th Asia and South Pacific Design Automation Conference

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Design and evaluation of shared buffer based NoC

Zhang

Hou

et al. 2009

2009 Asia-Pacific Conference on Computational Intelligence and Industrial Applications (PACIIA)

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II. NOC ARCHITECHTURE discussed, in section III, the method of buffer sharing between different channels was proposed, then in section IV, we introduce the monitor network, and use it to evaluate the performance of the on-chip network, and in section V an application of lPEG decoding was presented; finally in section VI, conclusion of the paper were presented.NoC consists of two primary function modules: resource element (RE) and communication element (CE). The NoC based MPSoC prototype proposed in this paper is shown in figure 1. RE consists of various IPs, including processor, memory, interrupt controller and so on, which connected by shared bus. The part of linking RE to CE is called resourcenetwork interface (RN!), which encapsulates the data from RE into packets, then transmits them at sending ends , and conversely on the receiving ends. CE , namely router, makes up of on-chip network and completes package switching. There, we use a 20 mesh topology for interconnection network, because of its flexibility to a 2-dimensional chip.'-"~Li nk i L .. ..! Figure 1 NoG prototype architecture RE In our design, we integrate 3x3 REs with a 3x3 routerbased on-chip network. Every router connects a RE by RNI. A RE is a sub-system which consists of an ARM compatible core , an interrupt controller, local memory and a RNI. To be noted, one of the REs (grey marked) is substituted with a specific display engine, for the sake of demo application. So the design consists in fact 8 ARM cores. Each RE accesses network via RNI. The RNI establishes the link between a router and a RE, it's responsible for packing and de-packing the data packets transferred on the network.The router forwards packets between different REs , it implements the function of routing, flow control, switching, arbitration, and buffering for the network communication.Abstract -New tendencie s envisage multiprocessor systems-onchips (MPSoCs) as a promising solution for high performance embedded System. And the key challenge is how to improve the communication efficiency . Network on Chip (NoC) has been considered as a new paradigm in the next generation communicat ion architecture for its scalability and power efficiency. A NoC prototype which consists of 8 ARM compatible cores and a routerbased on-chip network was designed and implemented on FPGA device. An application of lP EG decoding was fulfilled on this prototype and the task partition was discussed . Specially, a method of buffer sharing was proposed . Based on the method, buffer elements can be shared in part between different channels of the router. A well-designed on-chip monitoring network was implemented for Performance evaluation. Experiment results show that the buffer sharing method can save memory resource distinctly .

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Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip

McCanny

Sezer

2011

2011 IEEE International SOC Conference

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Design and performance evaluation of virtual-channel based NoC

Cited by 5 publications

References 7 publications

A performance enhanced dual-switch Network-on-Chip architecture

A performance enhanced dual-switch Network-on-Chip architecture

Design and evaluation of shared buffer based NoC

Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip

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