Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip

Lu, Ye; McCanny, J.V.; Sezer, Sakir

doi:10.1109/socc.2011.6085089

Cited by 16 publications

(10 citation statements)

References 14 publications

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“…Lu et al [5] proposed a low latency NoC router microarchitecture for FPGA-based implementation. In order to design a two-clock-cycle latency router, a parallel switch/VC allocator is proposed.…”

Section: Related Work On Low Latency Noc Routermentioning

confidence: 99%

“…In order to reduce on-chip memory usage, wormhole flow control algorithm is widely applied in NoC routers [2][3][4][5][6][7]. A wormhole router divides a packet into several smaller flow control digits (flits) and allows flits to be buffered in a flitserial fashion order through several routers along the path.…”

Section: Introductionmentioning

confidence: 99%

“…In this work, a microarchitecture for a low latency NoC router is proposed (this work is open source and is publicly released at http://opencores.org/project,an-fpga-implementation-oflow-latency-noc-based-mpsoc). The advantages of existing related works such as look-ahead routing computation [2,3], combination of VC/SW allocation [4,5,9], and replacing VC allocator with a queue of free VCs [3,6,9] are used. Meanwhile, several optimization techniques such as efficient masking of the allocation requests and broadcasting only two status bits instead of using proxy credit register have 2 International Journal of Reconfigurable Computing been applied to provide high operating frequency, reasonable hardware cost, and high utilization of the available buffer space.…”

Section: Introductionmentioning

confidence: 99%

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Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

Monemi

Ooi

Marsono

2015

International Journal of Reconfigurable Computing

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Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.

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Section: Related Work On Low Latency Noc Routermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

Monemi

Ooi

Marsono

2015

International Journal of Reconfigurable Computing

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“…In a 32-bit wide link, if = 10 −5 [9], the probability of = 2 is =2 = 4.96 × 10 −8 , while the probability of = 4 is =2 = 3.60×10 − 16 . This means that while it is possible to have links with high fault degrees in an NoC, the probability for this to happen in practical implementations is rather low.…”

Section: E Link Latencymentioning

confidence: 99%

“…To this end, we implemented all these four link fault-tolerant methods at RTL level by using Verilog HDL, and applied them in the context of the NoC platform developed by Lu et al [16]. The baseline router has 2 pipeline stages: look-ahead Routing Computation (RC) and combined VC/Switch Allocation (VA/SA) in the first stage, and Switch Traversal (ST) in the second stage.…”

Section: Performance Evaluationmentioning

confidence: 99%

A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip

Chen

Cotofana

2012

2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip

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Abstract-Aggressive MOS transistor size scaling substantially increase the probability of faults in NoC links due to manufacturing defects, process variations, and chip wire-out effects. Strategies have been proposed to tolerate faulty wires by replacing them with spare ones or by partially using the defective links. However, these strategies either suffer from high area and power overheads, or significantly increase the average network latency. In this paper, we propose a novel flit serialization method, which divides the links and flits into several sections, and serializes flit sections of adjacent flits to transmit them on all available fault-free link sections to avoid the complete waste of defective links bandwidth. Experimental results indicate that our method reduces the latency overhead significantly and enables graceful performance degradation, when compared with related partially faulty link usage proposals, and saves area and power overheads by up to 29% and 43.1%, respectively, when compared with spare wire replacement methods.

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An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs

Chen

Cotofana

2013

2013 Euromicro Conference on Digital System Design

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Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip

Cited by 16 publications

References 14 publications

Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip

An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs

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