Design and Performance of High-speed Low-Offset CMOS Double-Tail Dynamic Comparators using Offset Control scheme

Dubey, Avaneesh K.; Pal, Pratosh Kumar; Varshney, Vikrant; Kumar, Ankur; Nagaria, R. K.

doi:10.1109/iemeconx.2019.8876979

Cited by 5 publications

(1 citation statement)

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“…When clock signal is high (CLK1 = VDD), transistor Mc1 turns ON and M 3 , M 4 switch OFF. Nodes Y n and Y p based on the rates of the input voltages, begins to decline [20], [21]. The output terminals outp and outn will now start to get discharged from V DD at different rates while nodes C n and C p starts increasing from ground.…”

Section: Transconductance Enhanced Latched Dynamic Comparator (Teldc)mentioning

confidence: 99%

Performance and Design analysis of High Speed Charge Shared Dynamic Comparator for ADC Architecture in VLSI Application

Yadav

Wairya

2022

Preprint

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An ultimate requirement of the less power, high speed and energy efficient analog to digital converters (ADCs) have given immense popularity to dual stage positive feedback based dynamic regenerative clocked comparators. In this paper, a dynamic comparator based on shared charge logic is proposed. The latch of the proposed comparator uses a PMOS transistor, which greatly reduces delay and power consumption. This, design can operate at maximum frequency of 2GHz at supply voltage of 0.8V. This circuit is designed with CMOS 90nm and 45-nm technology along with implementation in CNTFET 10-nm technology. The proposed architecture consumes power of 3.3 µW and delay of 58.4ps at 0.8V supply voltage, 5mV input difference voltage, 0.7V common mode voltage. The power consumption is 81.4% less when compared with CNTFET based proposed architecture. Thus, CNTFET technology is proving to be power efficient and can operate at supply voltage as low as 0.4V.The Monte Carlo simulation of proposed architecture for power, delay, PDP and energy efficiency is also demonstrated in this paper along with process corner analysis. Monte Carlo simulations for mismatch analysis and input offset voltage for proposed comparator are done. Mathematical analysis is done for the delay of the proposed comparator. A high performing 3-bit Flash ADC architecture is implemented using proposed dynamic comparator. This Flash ADC architecture is simulated on 90nm technology which results in large reduction in static power consumption.

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Section: Transconductance Enhanced Latched Dynamic Comparator (Teldc)mentioning

confidence: 99%