2014
DOI: 10.3166/ejee.17.345-361
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Design and realization of deep trench superjunction diode for 600V applications

Abstract: The purpose of this paper is to present the Deep Trench SuperJunction Diode (DT-SJDiode) optimization and realization with a 600V breakdown voltage. We present technological and geometrical parameters influences on the breakdown voltage with simulations performed with Sentaurus TCAD. Previous works allowed to validate some critical technological process steps and to create a technological process for 1200V breakdown voltage applications. The main point here is to optimize those process steps (trench verticalit… Show more

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Cited by 3 publications
(3 citation statements)
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“…The DRIE process consists of multiple cycles of dry etching and passivation. The passivation layer suppresses the lateral etching of the silicon material and helps to form fine vertical trenches [34][35][36][37][38]. A p-type ion implantation is performed, which creates a p-type region under the trench with a certain lateral spread.…”
Section: Proposed Process Flowmentioning
confidence: 99%
“…The DRIE process consists of multiple cycles of dry etching and passivation. The passivation layer suppresses the lateral etching of the silicon material and helps to form fine vertical trenches [34][35][36][37][38]. A p-type ion implantation is performed, which creates a p-type region under the trench with a certain lateral spread.…”
Section: Proposed Process Flowmentioning
confidence: 99%
“…Nevertheless the fabrication of this structure is complex and requires multiple EPI steps. A proposed cost effective solution is to replace these multiple EPI layer by a single N type layer with deep trenches doped all around by P type implantation [10]. Breakdown Voltage depends on the size of the trenches as well as on the fine equilibrium between the N EPI and P implanted dopants.…”
Section: Low Dose Trench Doping For Superjunctions (Laas / Ibs Colmentioning
confidence: 99%
“…Although various termination structures can be employed in combination with the Si/SiC layers, the deep and wide trench structure, proposed in Fig. 1, is preferred due to its ultra-small area [1][2][3], e.g., typically 350 um in width in a 3300 V rated device , which is desired not only to reduce the chip cost but minimize the potential yield loss resulted from crystal defects during hetero-epitaxy. The improved characteristics and reliability of the new termination is studied in detail by extensive simulation and the data will be presented in the following paragraphs.…”
Section: Introductionmentioning
confidence: 99%