Design and Simulation Analysis of Semi-Active Lifting and Sinking Compensation System

Wang, Chuan; Liu, Huachuan; Zhang, Xueliang; Huang, Chi; Chen, Qiufan

doi:10.54097/ajst.v5i1.5392

Cited by 1 publication

(3 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A selection of these significant contributions is discussed herein. The state of the art relating to the FPGA implementation of various digital systems is described in several pieces of literature [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18], and a summary is provided in Table 1.…”

Section: Literature Reviewmentioning

confidence: 99%

“…In a similar vein to the study of Singh et al [12], Singh et al [17] proposed IP modeling-based power models for DSP blocks. Lastly, Huang [18] proposed a novel design and implementation of an IIC interface IP core, claiming reduced resource utilization with a complete range of functions, compared to existing similar IP cores. An extensive body of literature covers the FPGA implementation and subsequent analysis of performance parameters, either in isolation or in combination, such as area, power, and delay [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18].…”

Section: Literature Reviewmentioning

confidence: 99%

“…Lastly, Huang [18] proposed a novel design and implementation of an IIC interface IP core, claiming reduced resource utilization with a complete range of functions, compared to existing similar IP cores. An extensive body of literature covers the FPGA implementation and subsequent analysis of performance parameters, either in isolation or in combination, such as area, power, and delay [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. In addition, the literature is rich with studies on modular adders targeting standard cell ASICs [19][20][21][22].…”

Section: Literature Reviewmentioning

confidence: 99%

See 2 more Smart Citations

Performance Analysis of a Generic Modular Adder via RTL Programming and IP Modeling Techniques on FPGA

Gupta,

Verma,

Akhter

2023

ISI

View full text Add to dashboard Cite

The modular adder, a critical arithmetic component for residue calculations, is explored in this study through its implementation on a field programmable gate array (FPGA), specifically targeting the Xilinx Zynq-7000 family device. Recent literature reveals an innovative combination of parallel prefix addition and flagged prefix addition techniques for the design of the modular adder. The parallel prefix addition, an evolution of the carry look-ahead addition, utilizes the prefix operation, whereas the flagged prefix addition generates a novel set of intermediate outputs, namely flag bits, to execute the increment operation. This paper extends this innovative combination by demonstrating the FPGA implementation of the existing design via two distinct strategies. The first strategy employs a register-transfer level (RTL) description of the design using the very high-speed integrated circuit hardware description language (VHDL), while the second strategy deploys userdefined intellectual property (IP) blocks for the design implementation. FPGA area and power reports are subsequently generated using VIVADO IDE. The RTL approach illustrates an average savings of 14.30% in slice look-up tables (LUTs) utilization and 1.91% in slice flip-flops (FFs) utilization, suggesting its superiority for applications that prioritize area-efficiency. However, the IP modeling approach emerges as crucial for managing the perpetually increasing complexity of system-on-chip (SoC) designs.

show abstract