Design and simulation of all optical shift registers using D flip‐flop

Ramachandran, Manohari; Prince, Shanthi; Kambham, Archana; Maruthi, Naga

doi:10.1002/mop.32350

Cited by 9 publications

(2 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Flip flops are the basic tools to store digital data [18,19]. One bit of information can be stored in one flip-flop [20].…”

Section: Based D Flip-flopmentioning

confidence: 99%

Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

Devi¹,

Bhanumathi²

2022

Computers, Materials &Amp; Continua

View full text Add to dashboard Cite

Now a days, MOS Current Mode Logic (MCML) has emerged as a better alternative to Complementary Metal Oxide Semiconductor (CMOS) logic in digital circuits. Recent works have only traditional logic gates that have issues with information loss. Reversible logic is incorporated with MOS Current Mode Logic (MCML) in this proposed work to solve this problem, which is used for multiplier design, D Flip-Flop (DFF) and register. The minimization of power and area is the main aim of the work. In reversible logic, the count of outputs and inputs is retained as the same value for creating one-to-one mapping. A unique output vector set can be generated for each input vector set and information loss is also prevented. In reversible MCML based multiplier, reversible logic full adder is utilized to minimize the area and power. D flip-flops based on reversible MCML are often designed to store information that is then combined to form a reversible MCML based register. The proposed reversible MCML multiplier attains average power of 0.683 mW, Reversible MCML based DFF achieves 0.56 µW and Reversible MCML based 8-bit register attains 04.04 µW. The result shows that the proposed Reversible MCML based multiplier, Reversible MCML based D flip-flop and Reversible MCML based register achieves better performance in terms of current, power dissipation, average power and area.

show abstract

“…Flip flops are the basic tools to store digital data [18,19]. One bit of information can be stored in one flip-flop [20].…”

Section: Based D Flip-flopmentioning

confidence: 99%

Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

Devi¹,

Bhanumathi²

2022

Computers, Materials &Amp; Continua

View full text Add to dashboard Cite

show abstract

“…Ramachandran et al [21] presented the proposed design of all-optical shift registers by D flip-flop. All-optical shift registers are designed with interconnected D flip-flops and are operated by conventional clock pulses.…”

Section: Introductionmentioning

confidence: 99%

Adiabatic technique based low power synchronous counter design

Sanadhya

Sharma

Alfilh

2023

IJECE

View full text Add to dashboard Cite

<p>The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit synchronous counter based on the novel T flip-flops, a performance matrix such as PD, latency, and PDP is analyzed. The analysis is carried out at 100 and 10 MHz frequencies with varying temperatures and operating voltages. It is observed that the presented counter design has a lesser power requirement and PDP compared to the existing counter architectures. The proposed T-flip-flop design at the 45 nm technology node shows an improvement of 30%, 76%, and 85% in latency, PD, and PDP respectively to the 180 nm node at 10 MHz frequency. Similarly, the proposed counter at the 45 nm technology node shows 96% and 97% improvement in power dissipation, delay, and PDP respectively compared to the 180 nm at 10 MHz frequency.</p>

show abstract