Design and simulation of deep nanometer SRAM cells under energy, mismatch, and radiation constraints

Barrio, Pablo Royer del

doi:10.20868/upm.thesis.37474

Cited by 3 publications

(3 citation statements)

References 63 publications

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“…The read VTC is a plot of Qb-node voltage (VQb) versus Qb-node voltage (VQb) with BL, BLB WL are biased at VDD. The write VTC is obtained by sweeping the voltage at the storage Q-node with BL and WL biased at VDD, and BLB biased at the ground while plotting the node voltage at Qb-node [9], [13]- [18]. The width of the pull-up transistor is considered a Gaussian distribution function to perform Monte Carlo simulations to observe the effect of Write-ability due to the pull-up ratio (PR) variation.…”

Section: Write Static Noise Margin (Wsnm)mentioning

confidence: 99%

Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell

Chokkakula

Noorbasha

Murthy

2023

IJECE

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<span lang="EN-US">This paper presents a reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuit for the 9T Schmitt trigger-based static random-access memory (SRAM) cell (9T-ST), significantly improving write performance for real-time memory applications. In deep sub-micron technology, increasing device parameter deviations significantly reduce SRAM cells' write-ability. The proposed RNBLCS write-assist driver for 9T-ST SRAM cell has 0.84×, 0.48×, 0.27× optimized write access delay and 1.05×, 1.08×, 1.19× improvement in write static noise margin (WSNM), 1.05×, 1.13×, and 1.39× improvement in write margin (WM), 0.96×, 0.89× and 0.72× minimum write trip-point (WTP) from transient-negative bit line (Tran-NBL), capacitive charge sharing (CCS), and conventional write circuits respectively. The proposed RNBLCS is functionally verified using a synopsys custom compiler with a 16 nm BSIM4 model card for bulk complementary metal-oxide semiconductor (</span><span lang="EN-US">CMOS).</span>

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Section: Write Static Noise Margin (Wsnm)mentioning

confidence: 99%

Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell

Chokkakula

Noorbasha

Murthy

2023

IJECE

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“…The design of on-chip memory for SoC applications involves a delicate balance between high-speed performance and energy efficiency. Researchers and engineers continually explore a combination of architectural, circuit-level, and technology-specific innovations to address these challenges and deliver memory systems that meet the evolving requirements of modern computing applications [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

A novel design of collapsed supply and boosted bit-line swing write driver for fast write access 9T SRAM

Ganesh,

Sai Kumar,

Shoukath Vali

et al. 2024

Eng. Res. Express

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This work presents a collapsed supply and boosted bit-line swing (CSBBS) write driver circuit, with the specific goal of enhancing write performance. The write ability of SRAM cells is gravely affected by device parameter variations in deep sub-threshold region of operations. The collapsed supply and boosted bit-line swing are key features aimed at achieving improvements in speed and efficiency during the memory write process. In comparison to conventional, Ultra dynamic scaled supply write (UDSS), Negative charge-boosted bit line (NCBBL), and Reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuits, Proposed collapsed supply and boosted bit-line swing (CSBBS) for 9T SRAM cell has optimized write access delays of 0.74X, 0.41X, 0.32X and 0.21X, improvement in write margin (WM) of 1.51X, 1.34X, 1.22X and 1.12X respectively. The CSBBS Write driver circuit is implemented using custom compiler (Synopsys) through a 28nm BSIM4 model card for bulk CMOS. MC simulation results are monitored on Cosmoscope wave viewer (Synopsys).

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“…Another reliability concern getting higher importance in nanoscale design is the effect of radiation on circuits [26]. Energetic particles such as alpha particles from packaging material and neutrons from the atmosphere may generate electron-hole pairs as they pass through the semiconductor device [26]. Then the according accumulated charge may flip the state of SRAM cell and cause transient fault inside the memory.…”

Section: Reliability-aware Memory Design Using Advanced Reconfigurati...mentioning

confidence: 99%

Reliability-aware memory design using advanced reconfiguration mechanisms

Pouyan

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Fast and Complex Data Memory systems has become a necessity in modern computational units in today's integrated circuits. These memory systems are integrated in form of large embedded memory for data manipulation and storage. This goal has been achieved by the aggressive scaling of transistor dimensions to few nanometer (nm) sizes, though; such a progress comes with a drawback, making it critical to obtain high yields of the chips. Process variability, due to manufacturing imperfections, along with temporal aging, mainly induced by higher electric fields and temperature, are two of the more significant threats that can no longer be ignored in nano-scale embedded memory circuits, and can have high impact on their robustness. Static Random Access Memory (SRAM) is one of the most used embedded memories; generally implemented with the smallest device dimensions and therefore its robustness can be highly important in nanometer domain design paradigm. Their reliable operation needs to be considered and achieved both in cell and also in architectural SRAM array design. Recently, and with the approach to near/below 10nm design generations, novel non-FET devices such as Memristors are attracting high attention as a possible candidate to replace the conventional memory technologies. In spite of their favorable characteristics such as being low power and highly scalable, they also suffer with reliability challenges, such as process variability and endurance degradation, which needs to be mitigated at device and architectural level. This thesis work tackles such problem of reliability concerns in memories by utilizing advanced reconfiguration techniques. In both SRAM arrays and Memristive crossbar memories novel reconfiguration strategies are considered and analyzed, which can extend the memory lifetime. These techniques include monitoring circuits to check the reliability status of the memory units, and architectural implementations in order to reconfigure the memory system to a more reliable configuration before a fail happens. Actualmente, el diseño de sistemas de memoria en circuitos integrados busca continuamente que sean más rápidos y complejos, lo cual se ha vuelto de gran necesidad para las unidades de computación modernas. Estos sistemas de memoria están integrados en forma de memoria embebida para una mejor manipulación de los datos y de su almacenamiento. Dicho objetivo ha sido conseguido gracias al agresivo escalado de las dimensiones del transistor, el cual está llegando a las dimensiones nanométricas. Ahora bien, tal progreso ha conllevado el inconveniente de una menor fiabilidad, dado que ha sido altamente difícil obtener elevados rendimientos de los chips. La variabilidad de proceso - debido a las imperfecciones de fabricación - junto con la degradación de los dispositivos - principalmente inducido por el elevado campo eléctrico y altas temperaturas - son dos de las más relevantes amenazas que no pueden ni deben ser ignoradas por más tiempo en los circuitos embebidos de memoria, echo que puede tener un elevado impacto en su robusteza final. Static Random Access Memory (SRAM) es una de las celdas de memoria más utilizadas en la actualidad. Generalmente, estas celdas son implementadas con las menores dimensiones de dispositivos, lo que conlleva que el estudio de su robusteza es de gran relevancia en el actual paradigma de diseño en el rango nanométrico. La fiabilidad de sus operaciones necesita ser considerada y conseguida tanto a nivel de celda de memoria como en el diseño de arquitecturas complejas basadas en celdas de memoria SRAM. Actualmente, con el diseño de sistemas basados en dispositivos de 10nm, dispositivos nuevos no-FET tales como los memristores están atrayendo una elevada atención como posibles candidatos para reemplazar las actuales tecnologías de memorias convencionales. A pesar de sus características favorables, tales como el bajo consumo como la alta escabilidad, ellos también padecen de relevantes retos de fiabilidad, como son la variabilidad de proceso y la degradación de la resistencia, la cual necesita ser mitigada tanto a nivel de dispositivo como a nivel arquitectural. Con todo esto, esta tesis doctoral afronta tales problemas de fiabilidad en memorias mediante la utilización de técnicas de reconfiguración avanzada. La consideración de nuevas estrategias de reconfiguración han resultado ser validas tanto para las memorias basadas en celdas SRAM como en `memristive crossbar¿, donde se ha observado una mejora significativa del tiempo de vida en ambos casos. Estas técnicas incluyen circuitos de monitorización para comprobar la fiabilidad de las unidades de memoria, y la implementación arquitectural con el objetivo de reconfigurar los sistemas de memoria hacia una configuración mucho más fiables antes de que el fallo suceda

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Design and simulation of deep nanometer SRAM cells under energy, mismatch, and radiation constraints

Cited by 3 publications

References 63 publications

Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell

Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell

A novel design of collapsed supply and boosted bit-line swing write driver for fast write access 9T SRAM

Reliability-aware memory design using advanced reconfiguration mechanisms

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