Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections

Ginez, O.; Portal, J.M.; Müller, Christophe

doi:10.1109/ets.2009.23

Cited by 23 publications

(12 citation statements)

References 9 publications

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“…Table IV summarizes possible faults caused by corresponding transistor stuck-on (AT on ) and bridge defects, where x and y in W DF (x, y), dW DF (x, y), and CF st (x, y) denote the state of aggressor and victim. Some of faults are also defined in existing works [10]- [13]. However, we found two new faults, write disturbance fault (W DF ) and dynamic write disturbance fault (dW DF ), existing in 1T1R memristor memories.…”

Section: R(m)mentioning

confidence: 82%

“…Several works have addressed the defect analysis and testing of memristor memories [10]- [13]. In [10], a framework of defect oriented testing in 1R memristor memory based on electrical simulation was proposed.…”

Section: Introductionmentioning

confidence: 99%

“…Fault models incurred by parametric variation of a memristor are also considered. In [13], fault models of 1D1R memristor memories were investigated by considering bridge defects between two nodes.…”

Section: Introductionmentioning

confidence: 99%

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Fault modeling and testing of 1T1R memristor memories

Chen

2015

2015 IEEE 33rd VLSI Test Symposium (VTS)

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Memristor memory has attracted more attentions to act as one of future non-volatile memories. One access transistor and one memristor (1T1R) cell structure can be used to eliminate the issue of sneak path current of memristor memories with crossbar structure. In this paper, we propose several fault models for 1T1R memristor memories based on electrical defects, such as resistive bridge between two nodes, transistor stuck-on and stuckopen faults. In comparison with existing faults, two new faults, write disturbance fault (W DF ) and dynamic write disturbance fault (dW DF ), are found. In addition, a March test is proposed to cover the defined faults. The March test requires (1+2a+2b)N write operations and 5N read operations for an N -bit memristor memory, where a and b are the number of consecutive Write-1 and Write-0 operations for activating a dW DF .Index Terms-Non-volatile memory, memristor, resistive memory, test.

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Section: R(m)mentioning

confidence: 82%

Section: Introductionmentioning

confidence: 99%

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Fault modeling and testing of 1T1R memristor memories

Chen

2015

2015 IEEE 33rd VLSI Test Symposium (VTS)

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“…However, due to its immature manufacture process, memristive crossbar is prone to defects and requires efficient test methods for precise fault models with short test time. A number of test methods and fault models are proposed to test memristive crossbar [2,3,4,5] till now. The modeled faults can be classified as single-cell faults and coupling faults [2].…”

Section: Introductionmentioning

confidence: 99%

“…A coupling fault is defined as a transition in a cell (called aggressor cell) causing an unexpected change in another cell (called victim cell). In 1R crossbar, a coupling fault only occurs for the cells on adjacent wires in the same layer [4]. Kannan et al modeled the defects in a memristor caused by parametric variations during its fabrication [2].…”

Section: Introductionmentioning

confidence: 99%

Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm

Liu

You

Kuang

et al. 2015

IEICE Electron. Express

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Abstract:As an attractive option of future non-volatile memories (NVM), resistive random access memory (RRAM) has attracted more attentions. Due to its high density and low power, one memristor (1R) crossbar is a dominant RRAM structure. In this paper, we propose a logic operation-based design for testability (DFT) architecture for 1R crossbar testing. In this architecture, memristor-aided logic (MAGIC) NOR gates are embedded to check whether all the cells in the crossbar are 0 s or not at a time. A March-like test algorithm is also presented for the proposed architecture, which covers all modeled faults. The test time is reduced drastically with a little area overhead.

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