Design and Validation of Configurable Online Aging Sensors in Nanometer-Scale FPGAs

Valdes-Pena, Maria D.; Freijedo, J.; Rodriguez, Maria Jose Moure; Rodríguez-Andina, Juan J.; Semião, J.; Teixeira, Isabel Maria Cacho; Teixeira, J.P.; Vargas, F.

doi:10.1109/tnano.2013.2253795

Cited by 28 publications

(8 citation statements)

References 20 publications

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“…Also, the algorithm to reduce intra-chip variations make our PUF much more robust to the environmental fluctuation, which also enables a deployment of low overhead error correction schemes for robustness and stability of our PUFs. computer architecture design, temperature-aware 23 microprocessor design, reliable microprocessor 24 cache design, and hardware security. …”

Section: Discussionmentioning

confidence: 99%

“…For example, the adversary can try to use our aging algorithm in the opposite way, which may make the statistical property of our PUF worsened. One possible way to prevent this attack is to deploy aging sensors [23], [24], which can detect how much the circuit is aged by measuring the frequency of ring oscillators or delay elements. If the aging sensor detects a certain degree of the aging within a short time period, the OS can enforce the PUF to reside in a sleep mode so that the ALU can be cooled down and stop executing the malicious code.…”

Section: ) Malicious Usage Of Our Algorithmmentioning

confidence: 99%

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Processor-Based Strong Physical Unclonable Functions With Aging-Based Response Tuning

Kong¹,

Koushanfar²

2014

IEEE Trans. Emerg. Topics Comput.

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A strong physically unclonable function (PUF) is a circuit structure that extracts an exponential number of unique chip signatures from a bounded number of circuit components. The strong PUF unique signatures can enable a variety of low-overhead security and intellectual property protection protocols applicable to several computing platforms. This paper proposes a novel lightweight (low overhead) strong PUF based on the timings of a classic processor architecture. A small amount of circuitry is added to the processor for on-the-fly extraction of the unique timing signatures. To achieve desirable strong PUF properties, we develop an algorithm that leverages intentional post-silicon aging to tune the inter-and intrachip signatures variation. Our evaluation results show that the new PUF meets the desirable inter-and intrachip strong PUF characteristics, whereas its overhead is much lower than the existing strong PUFs. For the processors implemented in 45 nm technology, the average inter-chip Hamming distance for 32-bit responses is increased by 16.1% after applying our post-silicon tuning method; the aging algorithm also decreases the average intra-chip Hamming distance by 98.1% (for 32-bit responses).INDEX TERMS Physically unclonable function, multi-core processor, secure computing platform, postsilicon tuning, circuit aging, negative bias temperature instability. 16 2168-6750

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Section: Discussionmentioning

confidence: 99%

Section: ) Malicious Usage Of Our Algorithmmentioning

confidence: 99%

Processor-Based Strong Physical Unclonable Functions With Aging-Based Response Tuning

Kong¹,

Koushanfar²

2014

IEEE Trans. Emerg. Topics Comput.

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“…With the popularization of built-in self-tests (BISTs) in IC tests, actual on-chip measurements and sensor-based aging monitoring have become the mainstream methods [2,[9][10][11][12][13][14]26,27]. Naouss et al [2] established a low-cost test platform to evaluate FPGA reliability, which supports aging delay measurements for multiple FPGAs at the same time.…”

Section: Aging Tests On Fpgasmentioning

confidence: 99%

“…Hence, measuring the variations in path delay can quantify the aging degree of a circuit. For a long time, actual on-chip measurements and sensor-based aging monitoring have been the mainstream methods [2,[9][10][11][12][13][14]. Almost all of these methods employ ring oscillator (RO)based circuits to measure path delay.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

Huang

Wang

et al. 2022

Sensors

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Commercial off-the-shelf (COTS) field-programmable gate arrays (FPGAs) with a 28-nm process have become popular devices for computing systems. Although current generation FPGAs have advantages over previous models, the phenomenon of circuit aging has become more significant with the sharp reduction in the process size of FPGAs. Aging results in FPGA performance degradation over time and, ultimately, hard faults. However, few studies have focused on understanding aging mechanisms or estimating the aging trend of 28-nm FPGAs. For this, we used a ring oscillator (RO)-based test structure to extract data and build a dataset that could be used to predict aging trends and determine the primary aging mechanisms of 28-nm FPGAs. Moreover, we proposed a correction method to correct temperature-induced measurement errors in accelerated tests. Furthermore, we employed four machine learning (ML) technologies that were based on accurate measurement datasets to predict FPGA aging trends. In the experiment, 24 XILINX 7-series FPGAs (28 nm) were evaluated for 10+ years of circuit operation using accelerated tests. The results showed that the aging effects of negative-bias temperature instability (NBTI) was the primary aging mechanism. The correction method proposed in this paper could effectively eliminate measurement errors. In addition, the minimum prediction error rate of the ML model was only 0.292%.

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“…TEP circuits [1][2][3][4][5][6] predict a potential error by monitoring data signals. It flags a warning signal whenever the delayed data signals enter an erroneous timing zone that is defined with a clock signal.…”

Section: Introductionmentioning

confidence: 99%

A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

2020

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Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

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Design and Validation of Configurable Online Aging Sensors in Nanometer-Scale FPGAs

Cited by 28 publications

References 20 publications

Processor-Based Strong Physical Unclonable Functions With Aging-Based Response Tuning

Processor-Based Strong Physical Unclonable Functions With Aging-Based Response Tuning

Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

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