This paper presents approximate multipliers which are efficiently deployed on Field Programmable Gate Arrays (FPGAs) by using newly proposed approximate logic compressors at different levels of accuracy. Our approximate multiplier designs offer higher gains of power-delay-area products (PDAP) than those of the state-of-the-art works at comparable accuracies. Furthermore, in terms of delay, occupied area, and dynamic power dissipation, our designs are much better than Lookup Table based multiplier Intellectual Properties that are available on an FPGA. Particularly, our proposed 8-, 16-, and 32-bit multipliers can deliver PDAP gains up to 7.1 ×, 8.3 ×, and 5.0 ×, respectively. The effectiveness and applicability of our designs are also demonstrated by image processing applications such as image multiplication and sharpening. The experiments show that for the image sharpening, our 8 × 8 multipliers can deliver a good peak signal-to-noise ratio (PSNR) of 46.81 dB, a structural similarity index metric (SSIM) of 0.9989, and a dynamic power saving of up to 36.7% with regard to the exact multiplier. For the image multiplication, approximate 16 × 16 multipliers can offer a high PSNR of 80.25 dB, an SSIM of 1.0, and a dynamic power saving of up to 58.15%. From these demonstrations, the proposed multipliers are expected to be appropriate with high-performance and low-power error-resilient applications.INDEX TERMS Approximate computing, approximate compressor, error-resilient application, multiplier, power-delay-area product. I. INTRODUCTIONIn many of error-resilient applications such as multimedia, data mining, image processing, machine learning, etc., precise computations are not always necessary [1]- [4]. Computation results with some degradation of accuracy can be acceptable and meaningful enough for these applications [5]. By taking advantage of this property, therefore, we can take into consideration of trade-offs between the accuracy and electrical performances of a circuit. That is, we can sacrifice some loss of accuracy for beneficial gains of power dissipation, occupied area, and delay.Voltage over-scaling is a solution to reduce the power dissipation of a circuit [6]- [8]. However, when a circuit operates under the normal voltage level, timing-induced failures canThe associate editor coordinating the review of this manuscript and approving it for publication was Jenny Mahoney.

Overweight and obesity is an emerging public health problem among school-aged children in Bac Giang city in the Northen part of Vietnam recently. This study aims to identify overweight-obesity prevalence of secondary school children in this city and it’s associated factors. The study was a nested case control in a cross-sectional study design in 1528 secondary students selected from 4 secondary schools in 2 inner communes and 2 suburban communes of Bac Giang city, Vietnam. Result: Overweight prevalence among secondary school students in Bac Giang was 6.7%, the prevalence of obesity was 2.0%. Overweight and obesity is more prevalence in male students, inner communes and students from family have higher income and higher food expense. Overweight and obesity was associated with higher energy intake, more fat consumption, having supplement meals and bedtimemeal, increased physical activities and increased sleep duration. Conclusion: Education campaign targeting reducing overweight and obesity should target both parents about dietary adequacy and balance and children about more physical activities.

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In this paper, we propose a new method for measuring metastability in the mutual exclusion element (MUTEX) implemented on a Field Programmable Gate Array (FPGA). Our method uses fine-grained phase shifts of a digital clock manager to trigger Flip-Flops to generate concurrent inputs for a MUTEX. By dynamically adjusting the phase shift between two clock signals, we can force the MUTEX into a metastable state. The benefit of our approach is that it is easier to force the MUTEX become metastable compared to the conventional approach using two un-correlated signals. The experiments have been performed on a Xilinx Spartan-6 (XC6SLX9-4TQG144C).

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