Energy-Area-Efficient Approximate Multipliers for Error-Tolerant Applications on FPGAs

Toan, Nguyen Van; Lee, Jeong-Gun

doi:10.1109/socc46988.2019.1570548202

Cited by 9 publications

(2 citation statements)

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“…Compared to our previous study [25], this work contains several significant extensions as follows: (i) propose a newly designed approximate 4-2 compressor (CP2) to improve power consumption and area, (ii) formulate the error analysis of a large operand size multipliers being scaled up from smaller ones, (iii) develop large size multipliers (16 × 16, 32 × 32), (iv) extend the proposed approach to approximate signed multipliers, (v) develop image sharpening application to evaluate the effectiveness of approximate multipliers.…”

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confidence: 55%

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FPGA-Based Multi-Level Approximate Multipliers for High-Performance Error-Resilient Applications

Toan

Lee

2020

IEEE Access

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This paper presents approximate multipliers which are efficiently deployed on Field Programmable Gate Arrays (FPGAs) by using newly proposed approximate logic compressors at different levels of accuracy. Our approximate multiplier designs offer higher gains of power-delay-area products (PDAP) than those of the state-of-the-art works at comparable accuracies. Furthermore, in terms of delay, occupied area, and dynamic power dissipation, our designs are much better than Lookup Table based multiplier Intellectual Properties that are available on an FPGA. Particularly, our proposed 8-, 16-, and 32-bit multipliers can deliver PDAP gains up to 7.1 ×, 8.3 ×, and 5.0 ×, respectively. The effectiveness and applicability of our designs are also demonstrated by image processing applications such as image multiplication and sharpening. The experiments show that for the image sharpening, our 8 × 8 multipliers can deliver a good peak signal-to-noise ratio (PSNR) of 46.81 dB, a structural similarity index metric (SSIM) of 0.9989, and a dynamic power saving of up to 36.7% with regard to the exact multiplier. For the image multiplication, approximate 16 × 16 multipliers can offer a high PSNR of 80.25 dB, an SSIM of 1.0, and a dynamic power saving of up to 58.15%. From these demonstrations, the proposed multipliers are expected to be appropriate with high-performance and low-power error-resilient applications.INDEX TERMS Approximate computing, approximate compressor, error-resilient application, multiplier, power-delay-area product. I. INTRODUCTIONIn many of error-resilient applications such as multimedia, data mining, image processing, machine learning, etc., precise computations are not always necessary [1]- [4]. Computation results with some degradation of accuracy can be acceptable and meaningful enough for these applications [5]. By taking advantage of this property, therefore, we can take into consideration of trade-offs between the accuracy and electrical performances of a circuit. That is, we can sacrifice some loss of accuracy for beneficial gains of power dissipation, occupied area, and delay.Voltage over-scaling is a solution to reduce the power dissipation of a circuit [6]- [8]. However, when a circuit operates under the normal voltage level, timing-induced failures canThe associate editor coordinating the review of this manuscript and approving it for publication was Jenny Mahoney.

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“…FIGURE 5. Karnaugh map of the approximate 3-2 compressor: the outputs y 2 and y 1 have the same weight; the error cases are highlighted[25].…”

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confidence: 99%