Design and Verification of Advanced Microcontroller Bus Architecture-Advanced Peripheral Bus (AMBA-APB) Protocol

Jain, Padmaprabha; Rao, Satheesh

doi:10.1109/icicv50876.2021.9388549

Cited by 13 publications

(2 citation statements)

References 10 publications

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“…This increases the likelihood of bugs in the design appearing. As a result, the requirement for IC verification arose [41,42].…”

Section: Verificationmentioning

confidence: 99%

Development of SRAM-APB protocol interface and verification

Karthikeyan,

Balamurugan,

Rao Namamula

et al. 2023

Eng. Res. Express

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The purpose of this mechanism is to enhance the chip’s internal connections and read/write memory capabilities. The Advanced Microcontroller Bus Architecture (AMBA) is one such shared bus that uses static random-access memory to achieve this goal. As a result, it’s important to weigh a variety of design options before diving into the Verilog description. It’s also important to remember that the system must be designed to accommodate a large number of interoperable modules and memories. The design, on the other hand, starts with fewer modules and a less complicated description and realisation that relies on memory access. ModelSim is used to simulate after the delay has been modelled in Verilog. Since the interface’s static random-access memory uses an APB protocol, its performance may be tested at this stage. In addition, Questasim employs verification modules and System Verilog technologies to guarantee the system’s operation. From the obtained results, the Direct Memory Access (DMA) with SRAM-APB outperforms the alternatives, particularly in frame transmission schemes, with a wire efficiency that is 1.4 times higher and a dynamic energy efficiency that is nearly twice as high as those of conventional configurations.

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“…This increases the likelihood of bugs in the design appearing. As a result, the requirement for IC verification arose [41,42].…”

Section: Verificationmentioning

confidence: 99%

Development of SRAM-APB protocol interface and verification

Karthikeyan,

Balamurugan,

Rao Namamula

et al. 2023

Eng. Res. Express

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“…The list of signals in the APB interface is described in Table1. Any transfer through the APB bus happens in two cycles provided that the slave does not extend the transfer [4,5,6] UTAA (Unaligned To Aligned Access) bridge is implemented using a state machine [7]. Using a state machine, implementation of complex hardware logic becomes easier.…”

Section: Design Under Testmentioning

confidence: 99%

Design and Verification of Apb Bridge

2022

IRJMETS

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Semiconductor chips use a wide variety of communication protocols. Not all applications require a high-speed bus protocol. APB (Advanced Peripheral Bus) protocol from AMBA (Advanced Microcontroller Bus Architecture) family is an excellent choice where speed is not desired. APB protocol allows the address on this address bus to be unaligned to the width of the data bus. APB slave which receives this read/write request might not be capable of handling unaligned addresses. Its result might be unpredictable. This paper helps solve this limitation in the slave by adding a bridge that converts requests with an unaligned address from the master to two separate requests with addresses aligned to the data bus. Developing this bridge helps in reusing the APB slaves (which do not support unaligned addresses) and APB masters (which issue unaligned addresses). Using this bridge helps designers save a lot of time and energy which otherwise is spent making changes in APB slaves to support unaligned addresses or APB master to only send aligned addresses. And, to make sure that the bridge behaves as expected, verification is important. This paper talks about developing a verification environment using UVM (Universal Verification Methodology), which is reusable and easily manageable.

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