Design Automation of Low Dropout Voltage Regulators: A General Approach

Mohamed, Karimeldeen; Nafea, Sherif F.; Omran, Hesham

doi:10.3390/electronics12010205

Cited by 3 publications

(3 citation statements)

References 18 publications

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“…The CONTROL UNIT measures the energy accumulated during the harvesting process, and when it is enough to supply the INTERNAL UNIT, enables the transfer of the collected energy OWPT-Output to the LDO block. As reported in Figure 5, the LDO block is implemented by using a standard architecture, including a BJT-based voltage reference V re f [31]. The LDO block provides a 1.2 V single-supply voltage for a suitable period, performing the SLIPT system activation by using the RX-READY block.…”

Section: Design and Architecture Implementation Of The Slipt Systemmentioning

confidence: 99%

A 6 Mbps 7 pJ/bit CMOS Integrated Wireless Simultaneous Lightwave Information and Power Transfer System for Biomedical Implants

De Marcellis,

Di Patrizio Stanchieri,

Faccio

et al. 2024

Electronics

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This paper presents a Simultaneous Lightwave Information and Power Transfer (SLIPT) system for implantable biomedical applications composed of an external and internal (i.e., implantable) unit designed at a transistor level in TMSC 0.18 µm standard CMOS Si technology, requiring Si areas of 200 × 260 µm2 and 615 × 950 µm2, respectively. The SLIPT external unit employs a semiconductor laser to transmit data and power to the SLIPT internal unit, which contains an Optical Wireless Power Transfer (OWPT) module to supply its circuitry and, in particular, the data receiver module. To enable these operations, the transmitter module of the SLIPT external unit uses a novel reverse multilevel synchronized pulse position modulation technique based on dropping the laser driving current to zero so it produces laser pulses with a reversed intensity profile. This modulation technique allows: (i) the SLIPT external unit to code and transmit data packages of 6-bit symbols received and decoded by the SLIPT internal unit; and (ii) to supply the OWPT module also in the period between the transmission of two consecutive data packages. The receiver module operates for a time window of 12.5 µs every 500 µs, this being the time needed for the OWPT module to fully recover the energy to power the SLIPT internal unit. Post-layout simulations demonstrate that the proposed SLIPT system provides a final data throughput of 6 Mbps, an energy efficiency of 7 pJ/bit, and an OWPT module power transfer efficiency of 40%.

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Section: Design and Architecture Implementation Of The Slipt Systemmentioning

confidence: 99%

A 6 Mbps 7 pJ/bit CMOS Integrated Wireless Simultaneous Lightwave Information and Power Transfer System for Biomedical Implants

De Marcellis,

Di Patrizio Stanchieri,

Faccio

et al. 2024

Electronics

View full text Add to dashboard Cite

show abstract

“…In this scenario, the dependence of the device parameters on V DS and V SB is ignored [3]. A more accurate approach stores the device characteristics at the reference width in a precomputed lookup table (LUT) that has four-dimensions, namely, V GS , V DS , V SB , and L. The data in the LUT can be used to design the analog circuit using scripts and yields results that are very close to the final simulation results [2]- [7].…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we propose a practical and efficient approach for incorporating the LDEs due to N F and W F dependence in the methodology of MOSFET circuit sizing using precomputed LUTs. This serves towards more general use of the gm/ID methodology and the precomputed LUTs approach in systematic analog design while taking the layout dependent effects into consideration, which was not addressed in our previous work [3]- [7]. The proposed approach is based on creating a set of normalized auxiliary LUTs to correct the width-independent main LUT, while maintaining a small impact on the LUT size.…”

Section: Introductionmentioning

confidence: 99%

Capturing Layout Dependent Effects in MOSFET Circuit Sizing Using Precomputed Lookup Tables

et al. 2023

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Sizing analog circuits using precomputed look-up tables (LUTs) has recently gained traction for fast and systematic design-space exploration without a simulator in the loop. In its current form, the underlying g m /I D -based design methodology assumes that the MOSFET figures of merit are independent of absolute channel width. However, this assumption can introduce significant errors when the layoutdependent effects (LDEs) of modern CMOS technologies are considered. In this paper, an accurate and efficient procedure is developed that incorporates the dependence on the MOSFET width per finger and number of fingers in the precomputed LUTs. The proposed approach uses a set of normalized auxiliary LUTs to correct the device behavior with a subtle impact on the LUT size and the computational effort. Moreover, the nonlinear variation of the drain-to-bulk (c db ) and source-to-bulk (c sb ) capacitances with the device number of fingers is taken into account. The correction is based on precomputed simulation data and is thus independent of the model parameters and implementation. We present a track-and-hold circuit example that is sensitive to the width independence assumption, and show that the proposed fix prevents overdesign, resulting in a 44% reduction in switch area.INDEX TERMS gm/ID methodology, precomputed lookup tables, analog design automation, layout dependent effects (LDEs)

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Toward Memory-Efficient Analog Design Using Precomputed Lookup Tables

Omran

2024

Electronics

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Analog design productivity remains a challenge in the digitally driven semiconductor chip design field. Knowledge-based and simulation-based analog automation approaches have not achieved widespread acceptance in the analog design community. Systematic analog design using precomputed lookup tables (LUTs) is a promising approach that can address the design productivity challenge. Although modern computing systems have powerful memory capabilities, which make the LUT approach viable, reducing the memory footprint of the LUTs remains a challenge. A memory-efficient design technique using LUTs is proposed by using an incomplete grid in the MOSFET degrees-of-freedom (DoFs) space. An efficient indexing technique for the incomplete grid is also proposed, using a precomputed offset array in various scenarios, such as two-sided constraints and three-dimensional LUTs. The results show that the proposed technique can achieve up to a 67% reduction in memory footprint, in addition to improving LUT generation time and query performance.

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Design Automation of Low Dropout Voltage Regulators: A General Approach

Cited by 3 publications

References 18 publications

A 6 Mbps 7 pJ/bit CMOS Integrated Wireless Simultaneous Lightwave Information and Power Transfer System for Biomedical Implants

A 6 Mbps 7 pJ/bit CMOS Integrated Wireless Simultaneous Lightwave Information and Power Transfer System for Biomedical Implants

Capturing Layout Dependent Effects in MOSFET Circuit Sizing Using Precomputed Lookup Tables

Toward Memory-Efficient Analog Design Using Precomputed Lookup Tables

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