Analog design is an inherently intricate process comprising many trade-offs; as a result, it is an iterative time-consuming operation. A low dropout voltage regulator (LDO) is an example of such analog blocks that involve a myriad of trade-offs. In this paper, we present an automated design procedure for LDOs using precomputed look-up tables (LUTs) and the gm/ID methodology. Using a symbolic solver and the precomputed LUTs, a design database for an LDO that contains one million design points is generated in a few seconds. The database provides visualization of the design space and exploration of the trade-offs across different corners and load currents. A design example is provided to demonstrate the procedure using 40 nm technology and the results are verified using Cadence Spectre simulator. The approach is holistic in the sense that it uses an accurate symbolic solver to capture the small signal model complexities, incorporates LUTs for accurate calculation of the large signal solution and the small signal parameters, is fast because the simulator in the loop scenario is omitted, and almost all the specifications of LDOs are incorporated.

Sizing analog circuits using precomputed look-up tables (LUTs) has recently gained traction for fast and systematic design-space exploration without a simulator in the loop. In its current form, the underlying g m /I D -based design methodology assumes that the MOSFET figures of merit are independent of absolute channel width. However, this assumption can introduce significant errors when the layoutdependent effects (LDEs) of modern CMOS technologies are considered. In this paper, an accurate and efficient procedure is developed that incorporates the dependence on the MOSFET width per finger and number of fingers in the precomputed LUTs. The proposed approach uses a set of normalized auxiliary LUTs to correct the device behavior with a subtle impact on the LUT size and the computational effort. Moreover, the nonlinear variation of the drain-to-bulk (c db ) and source-to-bulk (c sb ) capacitances with the device number of fingers is taken into account. The correction is based on precomputed simulation data and is thus independent of the model parameters and implementation. We present a track-and-hold circuit example that is sensitive to the width independence assumption, and show that the proposed fix prevents overdesign, resulting in a 44% reduction in switch area.INDEX TERMS gm/ID methodology, precomputed lookup tables, analog design automation, layout dependent effects (LDEs)