Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM

Nomura, Tsuyoshi; Mori, Ryota; Takayanagi, Koji; Fukuoka, Kazuki; Nii, Koji

doi:10.1109/jetcas.2016.2547719

Cited by 3 publications

(1 citation statement)

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“…In [1,2], refresh-control systems that employ temperature sensors in both the DRAM and the processor die were proposed. In these systems, the refresh rates determined by the respective sensors are compared and a compromise refresh rate is determined.…”

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confidence: 99%

Dynamic voltage frequency scaling‐aware refresh management for 3D DRAM over processor architecture

Lim

Kim

et al. 2017

Electron. lett.

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Three-dimensional integrated systems that combine large-capacity dynamic random access memory (DRAM) with high-performance processors represent a promising solution to implementing high-performance computing. However, in such configurations stacked DRAM cells will inevitably be exposed to high temperatures generated by the processor, thereby necessitating DRAMs with high refresh rates driven by embedded temperature sensors. In this Letter, a thermally aware refresh-control method that accounts for abrupt changes in temperature and thermal distribution using low-power techniques such as dynamic voltage frequency scaling is proposed. Comparisons with previous systems via single-and eight-core simulations reveal that the proposed method improves efficiency with no additional overhead.

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confidence: 99%