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A Wide IO DRAM controller chip with Through Silicon Via (TSV) technology is implemented. Test circuitry for prebonding TSV tests are embedded in between the fine pitch TSVs. In order to reduce Vmin degradation induced by 512 DQs simultaneously switching noise, we introduce a package-board impedance optimization method utilizing a full digital noise monitor. We also develop a 3D stacked flip chip assembly process with void less underfill enabled by Non Conductive Film (NCF). 12.8 GB/s operation is achieved, while IO power was reduced by 89% compared to LPDDR3.

IntroductionThe demand for higher recording density and faster data transfer rate of magnetic storage devices continuouslv reauires the develomnent of new type of head technologies. Meta-ingap(M1G) heads were ir;troduced[l] to Gable a magnet:; recording head to write information on a high coercive media increasing the bit density on a track, and single crystal MIG technologies were later introduced[2] to improve the amplitude and SIN ratio of MIG heads.